Angelo Jacobo d6b6c0b9a4 added o_ddr3_clk port		2023-05-29 21:48:44 +08:00
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DDR3 SDRAM Verilog Model	readme file from Micron	2023-05-28 16:14:21 +08:00
ddr3_controller.v	fixed error "added_read_pipe has multiple drivers"	2023-05-29 20:52:48 +08:00
ddr3_phy.v	added 52ns sync reset (IDELAYCTRL requirement)	2023-05-29 16:19:32 +08:00
ddr3_top.v	added o_ddr3_clk port	2023-05-29 21:48:44 +08:00