UberDDR3/docs/ypcb-00338-1p1.md

YPCB-00338-1P1 DDR3 example

This board is an XC7K480T-FFG1156 design with two DDR3 channels. The example in example_demo/ypcb_00338_1p1 targets DDR3 channel 0 with a 64-bit data bus and uses UberDDR3's built-in BIST. The three user LEDs report:

• LED 0: PLL locked.
• LED 1: DDR3 calibration complete.
• LED 2: heartbeat after calibration.

The example uses the board's 50 MHz clock and generates a low-rate 25 MHz controller clock, 100 MHz DDR3 clock, 100 MHz 90-degree DDR3 clock, and 200 MHz reference clock. The low-rate configuration is intended as a bring-up target for open-source flows.

Build with OpenXC7:

cd example_demo/ypcb_00338_1p1
make openxc7

Program with:

make program

The pin constraints are derived from the LiteX-Boards ypcb_00338_1p1.py platform definition.