AngeloJacobo b9b49d67ab add xdc file used to test controller in Arty-S7		2023-11-09 14:16:46 +08:00
..
verilog-uart@1363dc7678	added uart submodule	2023-08-17 11:36:15 +08:00
Arty-S7-50-Master.xdc	add xdc file used to test controller in Arty-S7	2023-11-09 14:16:46 +08:00
arty_ddr3.v	fixed reset logic of _top, changed address accessed by ~	2023-11-09 14:13:08 +08:00