11 lines
772 B
Markdown
11 lines
772 B
Markdown
# DDR3_Controller (This repo will SOON be documented)
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# :construction: :construction_worker_man: :construction_worker_man: UNDER CONSTRUCTION :construction_worker_man: :construction_worker_man: :construction:
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Developer won't be available until end of October, but will be back by first week of November to continue this project. Planned improvements:
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- User documentation
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- More elaborated comments on the verilog file
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- AXI interface
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- Reduce logic resource (by optimizing logic and by making some parts removable)
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- Pass hardware test for Arty S7 FPGA board (this is currently passing on a Kintex S7 FPGA board but ironically not yet fully tested on an Arty S7 since it does not have ODELAY which makes it unable to do write calibration FOR NOW)
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- and a lot more....
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