UberDDR3/example_demo/arty_s7
AngeloJacobo 30731d1b4c add files for caas and linked uberddr3 files 2026-01-11 13:30:06 +08:00
..
Makefile added vivado on makefile (make vivado) 2025-05-12 16:02:38 +08:00
arty_ddr3.v run @ 100MHz with yosys 2025-12-31 14:39:16 +08:00
arty_ddr3.xdc fix flagged errors from openxc7 2025-03-02 14:34:59 +08:00
arty_ddr3_openxc7.bit run @ 100MHz with yosys 2025-12-31 14:39:16 +08:00
arty_ddr3_vivado.xdc added vivado on makefile (make vivado) 2025-05-12 16:02:38 +08:00
caas.conf add files for caas and linked uberddr3 files 2026-01-11 13:30:06 +08:00
clk_wiz.v run @ 100MHz with yosys 2025-12-31 14:39:16 +08:00
ddr3_controller.v add files for caas and linked uberddr3 files 2026-01-11 13:30:06 +08:00
ddr3_phy.v add files for caas and linked uberddr3 files 2026-01-11 13:30:06 +08:00
ddr3_top.v add files for caas and linked uberddr3 files 2026-01-11 13:30:06 +08:00
uart_rx.v add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00
uart_tx.v add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00