UberDDR3/example_demo/arty_s7
AngeloJacobo 9fd104b566 updated example demo bitstream files 2025-05-11 20:11:05 +08:00
..
Makefile add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00
arty_ddr3.bit updated example demo bitstream files 2025-05-11 20:11:05 +08:00
arty_ddr3.v fix flagged errors from openxc7 2025-03-02 14:34:59 +08:00
arty_ddr3.xdc fix flagged errors from openxc7 2025-03-02 14:34:59 +08:00
clk_wiz.v replace clock wizard with PLL 2024-06-09 15:31:27 +08:00
uart_rx.v add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00
uart_tx.v add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00