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Opensource DDR3 Controller
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Verilog 58.7%
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Angelo Jacobo 9be5b5a616
Update ddr3_controller.v 		2023-05-11 14:49:47 +08:00
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LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-04-27 20:02:37 +08:00
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README.md

DDR3_Controller

🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧

Sequential Read

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Sequential Read then Sequential Write

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Random Access

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Sequential Read Until Next Bank

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PHY Interface

WRITE OPERATION

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Sequential Write

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BITSLIP_DQS_TRAIN STATE:

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MPR_READ STATE:

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BITSLIP_DQ_TRAIN STATE:

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Sequential Read:

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