UberDDR3/rtl
AngeloJacobo f80d4ac21b simulation passing for ECC_ENABLE = 3 2024-07-15 18:31:49 +08:00
..
axi add copyright on headers 2024-06-09 12:01:30 +08:00
ecc resolve verilator lint flags 2024-06-24 17:16:26 +08:00
ddr3_controller.v simulation passing for ECC_ENABLE = 3 2024-07-15 18:31:49 +08:00
ddr3_phy.v add copyright on headers 2024-06-09 12:01:30 +08:00
ddr3_top.v add initial ECC, ECC_ENABLE = 2 working 2024-06-17 16:25:06 +08:00