AngeloJacobo 94b4e0866b added UART for debugging, DQ now support 1 cycle late		2025-03-02 14:15:44 +08:00
..
axi	update UberDDR3 AXI for Vivado custom IP	2025-02-16 14:53:05 +08:00
ecc	Revert "add self-refresh option, passing Simulation, ongoing formal"	2024-11-23 11:43:05 +08:00
spd	added simulation and project demo with XADC	2025-01-12 14:55:43 +08:00
ddr3_controller.v	added UART for debugging, DQ now support 1 cycle late	2025-03-02 14:15:44 +08:00
ddr3_phy.v	uncommented default_nettype	2025-03-01 19:32:35 +08:00
ddr3_top.v	uncommented default_nettype	2025-03-01 19:32:35 +08:00