UberDDR3/rtl
AngeloJacobo a80bacb718 add reset control from controller to phy 2023-09-15 19:59:39 +08:00
..
ddr3_controller.v now passes internal test calibration on klusterboard 2023-09-15 19:58:12 +08:00
ddr3_phy.v now passes internal test calibration on klusterboard 2023-09-15 19:58:36 +08:00
ddr3_top.v add reset control from controller to phy 2023-09-15 19:59:39 +08:00
fwb_slave.v make stall and accessible outside, removed added assumptions with i_slave_busy 2023-07-13 18:48:34 +08:00