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luke
/
UberDDR3
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https://github.com/AngeloJacobo/UberDDR3.git
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Opensource DDR3 Controller
controller
ddr3
ddr3-controller
ddr3-phy
fpga
memory-controller
phy
verilog
29
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6
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0
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65
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Verilog
58.7%
SystemVerilog
21.3%
Tcl
15.6%
Makefile
1.7%
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1.3%
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1.4%
7c47580d4d
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Angelo Jacobo
7c47580d4d
Delete formal_cover.gtkw
2023-04-06 19:44:30 +08:00
rtl
Update ddr3_controller.v
2023-04-06 19:43:32 +08:00
LICENSE
changed license to Apache 2.0
2023-03-23 20:18:46 +08:00
README.md
Update README.md
2023-04-06 19:41:57 +08:00
ddr3_controller.sby
removed parameter file "ddr3_parameters.vh"
2023-03-09 18:16:01 +08:00
run.sh
include directory on iverilog command
2023-03-02 20:20:14 +08:00
README.md
DDR3_Controller
🚧
👷♂️
👷♂️
UNDER CONSTRUCTION
👷♂️
👷♂️
🚧
Sequential Read
Sequential Read then Sequential Write
Random Access
Sequential Read Until Next Bank