UberDDR3/rtl
AngeloJacobo 66f0daf0e9 added AXI4 feature 2024-06-01 15:30:15 +08:00
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axi_addr.v added AXI4 feature 2024-06-01 15:30:15 +08:00
axim2wbsp.v added AXI4 feature 2024-06-01 15:30:15 +08:00
aximrd2wbsp.v added AXI4 feature 2024-06-01 15:30:15 +08:00
aximwr2wbsp.v added AXI4 feature 2024-06-01 15:30:15 +08:00
ddr3_controller.v clean verilator lint by making parameters integer (instead of being inferred as real) 2024-05-24 22:43:34 +08:00
ddr3_phy.v fixed rtoi error in vivado 2024-04-20 12:20:20 +08:00
ddr3_top.v fixed BYTE_LANES 2024-05-05 14:03:51 +08:00
ddr3_top_axi.v added AXI4 feature 2024-06-01 15:30:15 +08:00
fwb_slave.v make stall and accessible outside, removed added assumptions with i_slave_busy 2023-07-13 18:48:34 +08:00
migsdram.v added AXI4 feature 2024-06-01 15:30:15 +08:00
sfifo.v added AXI4 feature 2024-06-01 15:30:15 +08:00
skidbuffer.v added AXI4 feature 2024-06-01 15:30:15 +08:00
wbarbiter.v added AXI4 feature 2024-06-01 15:30:15 +08:00