63 lines
2.6 KiB
Markdown
63 lines
2.6 KiB
Markdown
# DDR3_Controller
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# :construction: :construction_worker_man: :construction_worker_man: UNDER CONSTRUCTION :construction_worker_man: :construction_worker_man: :construction:
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## Sequential Read
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## Sequential Read then Sequential Write
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## Random Access
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## Sequential Read Until Next Bank
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# PHY Interface
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## WRITE OPERATION
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## Sequential Write
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## BITSLIP_DQS_TRAIN STATE:
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## MPR_READ STATE:
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## BITSLIP_DQ_TRAIN STATE:
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## Sequential Read:
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## PER LANE READ CALIBRATION
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## AFTER READ CALIBRATION
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## LANES NOT IN SYNC
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## SAMPLE READ 1
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## SAMPLE READ 2 (UNIFORM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)
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## SAMPLE READ 3 (UNIFORM DELAY DIFFERENCE, 2 slow_clk ABSOLUTE DELAY)
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## SAMPLE READ 3 (RANDOM DELAY DIFFERENCE, 0 slow_clk ABSOLUTE DELAY)
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