AngeloJacobo 2e6c2183aa added sim duration for possible bus delays		2023-06-08 13:55:20 +08:00
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DDR3 SDRAM Verilog Model	added sim duration for possible bus delays	2023-06-08 13:55:20 +08:00
ddr3_controller.v	made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq	2023-06-08 11:01:56 +08:00
ddr3_phy.v	made delay tap loadable	2023-06-08 13:52:04 +08:00
ddr3_top.v	added wires for loadingg delay tap	2023-06-08 13:53:07 +08:00