Angelo Jacobo 1e89a236df fixed implementation errors in Vivado		2023-05-25 19:13:30 +08:00
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DDR3 SDRAM Verilog Model	Add files via upload	2023-05-18 10:50:30 +08:00
ddr3_controller.v	fixed implementation errors in Vivado	2023-05-25 19:13:30 +08:00
sdram.txt	Add files via upload	2023-05-22 19:53:20 +08:00
ug586_7Series_MIS.pdf	Add files via upload	2023-05-18 11:02:40 +08:00