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UberDDR3
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Opensource DDR3 Controller
20 Commits 6 Branches 0 Tags 65 MiB
Verilog 58.7%
SystemVerilog 21.3%
Tcl 15.6%
Makefile 1.7%
Shell 1.3%
Other 1.4%
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Angelo Jacobo 192a9950e4
applied :retab 		2023-03-30 18:27:58 +08:00
rtl applied :retab 2023-03-30 18:27:58 +08:00
LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-03-13 14:40:46 +08:00
ddr3_controller.sby removed parameter file "ddr3_parameters.vh" 2023-03-09 18:16:01 +08:00
formal_cover.gtkw added gtkwave template 2023-03-30 18:19:14 +08:00
run.sh include directory on iverilog command 2023-03-02 20:20:14 +08:00

README.md

DDR3_Controller

🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧