AngeloJacobo 22f6db696c automatically generate CL and CWL value based on ddr3 clock period		2024-05-05 15:21:55 +08:00
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ddr3_controller.v	automatically generate CL and CWL value based on ddr3 clock period	2024-05-05 15:21:55 +08:00
ddr3_phy.v	fixed rtoi error in vivado	2024-04-20 12:20:20 +08:00
ddr3_top.v	fixed BYTE_LANES	2024-05-05 14:03:51 +08:00
fwb_slave.v	make stall and accessible outside, removed added assumptions with i_slave_busy	2023-07-13 18:48:34 +08:00