AngeloJacobo 0b7d07e133 delete old bit and debug files		2023-11-09 14:14:27 +08:00
..
verilog-uart@1363dc7678	added uart submodule	2023-08-17 11:36:15 +08:00
arty_ddr3.v	fixed reset logic of _top, changed address accessed by ~	2023-11-09 14:13:08 +08:00