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UberDDR3
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vivado simulation files directory are now relative, can now run sim anywhere

This commit is contained in:
AngeloJacobo 2025-03-01 14:39:54 +08:00
parent af48f1fa08
commit f10fc7d10b
2 changed files with 16 additions and 16 deletions
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14
testbench/xsim/file_info.txt
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@ -1,7 +1,7 @@
ddr3_controller.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench"
ddr3_phy.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench"
ddr3_top.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" ddr3_top.v,verilog,xil_defaultlib,../../rtl/ddr3_top.v,incdir="../../testbench"
ddr3.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" ddr3.sv,systemverilog,xil_defaultlib,../../testbench/ddr3.sv,incdir="../../testbench"
ddr3_module.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" ddr3_module.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_module.sv,incdir="../../testbench"
ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_dimm_micron_sim.sv,incdir="../../testbench"
glbl.v,Verilog,xil_defaultlib,/home/ajacobo/incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"/glbl.v glbl.v,Verilog,xil_defaultlib

18
testbench/xsim/vlog.prj
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@ -1,13 +1,13 @@
verilog xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \ verilog xil_defaultlib --include "../../testbench" \
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v" \ "../../rtl/ddr3_controller.v" \
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v" \ "../../rtl/ddr3_phy.v" \
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v" \ "../../rtl/ddr3_top.v" \
sv xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \ sv xil_defaultlib --include "../../testbench" \
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv" \ "../../testbench/ddr3.sv" \
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv" \ "../../testbench/ddr3_module.sv" \
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv" \ "../../testbench/ddr3_dimm_micron_sim.sv" \
verilog xil_defaultlib "/home/ajacobo/Desktop/UberDDR3/testbench/xsim/glbl.v" verilog xil_defaultlib "../../testbench/xsim/glbl.v"
nosort nosort