diff --git a/testbench/xsim/file_info.txt b/testbench/xsim/file_info.txt
index 7c471d7..81e40b1 100644
--- a/testbench/xsim/file_info.txt
+++ b/testbench/xsim/file_info.txt
@@ -1,7 +1,7 @@
-ddr3_controller.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
-ddr3_phy.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
-ddr3_top.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
-ddr3.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
-ddr3_module.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
-ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
-glbl.v,Verilog,xil_defaultlib,/home/ajacobo/incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"/glbl.v
+ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench"
+ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench"
+ddr3_top.v,verilog,xil_defaultlib,../../rtl/ddr3_top.v,incdir="../../testbench"
+ddr3.sv,systemverilog,xil_defaultlib,../../testbench/ddr3.sv,incdir="../../testbench"
+ddr3_module.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_module.sv,incdir="../../testbench"
+ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_dimm_micron_sim.sv,incdir="../../testbench"
+glbl.v,Verilog,xil_defaultlib
diff --git a/testbench/xsim/vlog.prj b/testbench/xsim/vlog.prj
index 09d5fa1..d4ee2dc 100644
--- a/testbench/xsim/vlog.prj
+++ b/testbench/xsim/vlog.prj
@@ -1,13 +1,13 @@
-verilog xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \
-"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v" \
-"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v" \
-"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v" \
+verilog xil_defaultlib --include "../../testbench" \
+"../../rtl/ddr3_controller.v" \
+"../../rtl/ddr3_phy.v" \
+"../../rtl/ddr3_top.v" \
 
-sv xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \
-"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv" \
-"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv" \
-"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv" \
+sv xil_defaultlib --include "../../testbench" \
+"../../testbench/ddr3.sv" \
+"../../testbench/ddr3_module.sv" \
+"../../testbench/ddr3_dimm_micron_sim.sv" \
 
-verilog xil_defaultlib "/home/ajacobo/Desktop/UberDDR3/testbench/xsim/glbl.v"
+verilog xil_defaultlib "../../testbench/xsim/glbl.v"
 
 nosort