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use SIM_MODEL directive to use models during vivado simulation

This commit is contained in:
AngeloJacobo 2025-05-25 09:03:16 +08:00
parent a33560122c
commit e5bd0d74c3
7 changed files with 176 additions and 37 deletions
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204
rtl/ddr3_phy.v
View File

@ -181,7 +181,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("SDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, SDR
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
@ -231,7 +235,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("SDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, SDR
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
@ -305,7 +313,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -352,7 +364,11 @@ module ddr3_phy #(
//Delay the DQ
// Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
(* IODELAY_GROUP="DDR3-GROUP" *)
ODELAYE2_model #(
`ifndef SIM_MODEL
ODELAYE2 #(
`else
ODELAYE2_model #(
`endif
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
.ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
@ -380,12 +396,20 @@ module ddr3_phy #(
// OBUFDS: Differential Output Buffer
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
OBUFDS_model OBUFDS0_inst (
`ifndef SIM_MODEL
OBUFDS OBUFDS0_inst (
`else
OBUFDS_model OBUFDS0_inst (
`endif
.O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
.OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
.I(ddr3_clk_delayed) // Buffer input
);
OBUFDS_model OBUFDS1_inst (
`ifndef SIM_MODEL
OBUFDS OBUFDS1_inst (
`else
OBUFDS_model OBUFDS1_inst (
`endif
.O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
.OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
.I(ddr3_clk_delayed) // Buffer input
@ -396,7 +420,11 @@ module ddr3_phy #(
// OBUFDS: Differential Output Buffer
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
OBUFDS_model OBUFDS_inst (
`ifndef SIM_MODEL
OBUFDS OBUFDS_inst (
`else
OBUFDS_model OBUFDS_inst (
`endif
.O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
.OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
.I(ddr3_clk_delayed) // Buffer input
@ -411,12 +439,20 @@ module ddr3_phy #(
// OBUFDS: Differential Output Buffer
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
OBUFDS_model OBUFDS0_inst (
`ifndef SIM_MODEL
OBUFDS OBUFDS0_inst (
`else
OBUFDS_model OBUFDS0_inst (
`endif
.O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
.OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
.I(!i_ddr3_clk) // Buffer input
);
OBUFDS_model OBUFDS1_inst (
`ifndef SIM_MODEL
OBUFDS OBUFDS1_inst (
`else
OBUFDS_model OBUFDS1_inst (
`endif
.O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
.OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
.I(!i_ddr3_clk) // Buffer input
@ -427,7 +463,11 @@ module ddr3_phy #(
// OBUFDS: Differential Output Buffer
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
OBUFDS_model OBUFDS_inst (
`ifndef SIM_MODEL
OBUFDS OBUFDS_inst (
`else
OBUFDS_model OBUFDS_inst (
`endif
.O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
.OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
.I(!i_ddr3_clk) // Buffer input
@ -445,7 +485,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -495,7 +539,11 @@ module ddr3_phy #(
//Delay the DQ
// Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
(* IODELAY_GROUP="DDR3-GROUP" *)
ODELAYE2_model #(
`ifndef SIM_MODEL
ODELAYE2 #(
`else
ODELAYE2_model #(
`endif
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
.ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
@ -525,7 +573,11 @@ module ddr3_phy #(
// May only be placed in High Performance (HP) Banks
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
IOBUF_DCIEN_model #(
`ifndef SIM_MODEL
IOBUF_DCIEN #(
`else
IOBUF_DCIEN_model #(
`endif
.IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
.SLEW("FAST"), // Specify the output slew rate
.USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
@ -544,7 +596,11 @@ module ddr3_phy #(
// IOBUF: Single-ended Bi-directional Buffer
//All devices
// Xilinx HDL Libraries Guide, version 13.4
IOBUF_model #(
`ifndef SIM_MODEL
IOBUF #(
`else
IOBUF_model #(
`endif
//.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
//.IOSTANDARD("SSTL15"), // Specify the I/O standard
@ -561,7 +617,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -607,7 +667,11 @@ module ddr3_phy #(
// IOBUF: Single-ended Bi-directional Buffer
//All devices
// Xilinx HDL Libraries Guide, version 13.4
IOBUF_model #(
`ifndef SIM_MODEL
IOBUF #(
`else
IOBUF_model #(
`endif
//.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
//.IOSTANDARD("SSTL15"), // Specify the I/O standard
@ -624,7 +688,11 @@ module ddr3_phy #(
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
(* IODELAY_GROUP="DDR3-GROUP" *)
IDELAYE2_model #(
`ifndef SIM_MODEL
IDELAYE2 #(
`else
IDELAYE2_model #(
`endif
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
@ -653,7 +721,11 @@ module ddr3_phy #(
// ISERDESE2: Input SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
ISERDESE2_model #(
`ifndef SIM_MODEL
ISERDESE2 #(
`else
ISERDESE2_model #(
`endif
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
@ -726,7 +798,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -776,7 +852,11 @@ module ddr3_phy #(
//Delay the DQ
// Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
(* IODELAY_GROUP="DDR3-GROUP" *)
ODELAYE2_model #(
`ifndef SIM_MODEL
ODELAYE2 #(
`else
ODELAYE2_model #(
`endif
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
.ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
@ -803,7 +883,11 @@ module ddr3_phy #(
// OBUF: Single-ended Output Buffer
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
OBUF_model #(
`ifndef SIM_MODEL
OBUF #(
`else
OBUF_model #(
`endif
//.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
.SLEW("FAST") // Specify the output slew rate
) OBUF_dm (
@ -816,7 +900,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -862,7 +950,11 @@ module ddr3_phy #(
// OBUF: Single-ended Output Buffer
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
OBUF_model #(
`ifndef SIM_MODEL
OBUF #(
`else
OBUF_model #(
`endif
//.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
.SLEW("FAST") // Specify the output slew rate
) OBUF_dm (
@ -881,7 +973,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -930,7 +1026,11 @@ module ddr3_phy #(
// Xilinx HDL Libraries Guide, version 13.4
//Delay the DQ
(* IODELAY_GROUP="DDR3-GROUP" *)
ODELAYE2_model #(
`ifndef SIM_MODEL
ODELAYE2 #(
`else
ODELAYE2_model #(
`endif
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
@ -960,7 +1060,11 @@ module ddr3_phy #(
// May only be placed in High Performance (HP) Banks
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
IOBUFDS_DCIEN_model #(
`ifndef SIM_MODEL
IOBUFDS_DCIEN #(
`else
IOBUFDS_DCIEN_model #(
`endif
.IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
.SLEW("FAST"), // Specify the output slew rate
.USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
@ -980,7 +1084,11 @@ module ddr3_phy #(
// IOBUFDS: Differential Bi-directional Buffer
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
IOBUFDS_model #(
`ifndef SIM_MODEL
IOBUFDS #(
`else
IOBUFDS_model #(
`endif
//.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
.IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
//.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
@ -1000,7 +1108,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -1046,7 +1158,11 @@ module ddr3_phy #(
// IOBUFDS: Differential Bi-directional Buffer
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
IOBUFDS_model #(
`ifndef SIM_MODEL
IOBUFDS #(
`else
IOBUFDS_model #(
`endif
//.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
.IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
//.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
@ -1065,7 +1181,11 @@ module ddr3_phy #(
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
(* IODELAY_GROUP="DDR3-GROUP" *)
IDELAYE2_model #(
`ifndef SIM_MODEL
IDELAYE2 #(
`else
IDELAYE2_model #(
`endif
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
@ -1095,7 +1215,11 @@ module ddr3_phy #(
// ISERDESE2: Input SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
ISERDESE2_model #(
`ifndef SIM_MODEL
ISERDESE2 #(
`else
ISERDESE2_model #(
`endif
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
@ -1186,7 +1310,11 @@ module ddr3_phy #(
// ISERDESE2: Input SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
ISERDESE2_model #(
`ifndef SIM_MODEL
ISERDESE2 #(
`else
ISERDESE2_model #(
`endif
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
@ -1252,7 +1380,11 @@ module ddr3_phy #(
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2_model #(
`ifndef SIM_MODEL
OSERDESE2 #(
`else
OSERDESE2_model #(
`endif
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
@ -1305,7 +1437,11 @@ module ddr3_phy #(
// 7 Series
// Xilinx HDL Libraries Guide, version 13.4
(* IODELAY_GROUP="DDR3-GROUP" *)
IDELAYCTRL_model IDELAYCTRL_inst (
`ifndef SIM_MODEL
IDELAYCTRL IDELAYCTRL_inst (
`else
IDELAYCTRL_model IDELAYCTRL_inst (
`endif
.RDY(idelayctrl_rdy), // 1-bit output: Ready output
.REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.
.RST(sync_rst) // 1-bit input: Active high reset input, To ,Minimum Reset pulse width is 52ns

1
testbench/icarus_sim/regression_test_icarus.sh
View File

@ -55,6 +55,7 @@ fi
# Loop over each test configuration
index=1
rm -f *.log
for TEST in "${TESTS[@]}"; do
# Parse the test configuration into individual variables
read -r CONTROLLER_CLK_PERIOD DDR3_CLK_PERIOD ODELAY_SUPPORTED LANES_OPTION ADD_BUS_DELAY BIST_MODE <<< "$TEST"

3
testbench/icarus_sim/sim_icarus.sh
View File

@ -1,13 +1,14 @@
rm -rf ./uberddr3_sim ./sim.log
iverilog -o uberddr3_sim -g2012 \
-DNO_TEST_MODEL \
-DSIM_MODEL \
-s ddr3_dimm_micron_sim \
-I ../ \
../ddr3_dimm_micron_sim.sv \
../ddr3.sv \
../models/IDELAYCTRL_model.v \
../models/IDELAYE2_model.v \
../models/IOBUF_DCIEN.v \
../models/IOBUF_DCIEN_model.v \
../models/IOBUF_model.v \
../models/IOBUFDS_DCIEN_model.v \
../models/IOBUFDS_model.v \

0
testbench/models/IOBUF_DCIEN.v → testbench/models/IOBUF_DCIEN_model.v
View File

2
testbench/xsim/ddr3_dimm_micron_sim.sh
View File

@ -40,7 +40,7 @@ run()
# RUN_STEP: <compile>
compile()
{
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
xvlog --define SIM_MODEL $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
}
# RUN_STEP: <elaborate>

1
testbench/xsim/regression_test_vivado.sh
View File

@ -55,6 +55,7 @@ fi
# Loop over each test configuration
index=1
rm -f *.log
for TEST in "${TESTS[@]}"; do
# Parse the test configuration into individual variables
read -r CONTROLLER_CLK_PERIOD DDR3_CLK_PERIOD ODELAY_SUPPORTED LANES_OPTION ADD_BUS_DELAY BIST_MODE <<< "$TEST"

2
testbench/xsim/vlog.prj
View File

@ -1,7 +1,7 @@
verilog xil_defaultlib --include "../../testbench" \
"../../testbench/models/IDELAYCTRL_model.v" \
"../../testbench/models/IDELAYE2_model.v" \
"../../testbench/models/IOBUF_DCIEN.v" \
"../../testbench/models/IOBUF_DCIEN_model.v" \
"../../testbench/models/IOBUF_model.v" \
"../../testbench/models/IOBUFDS_DCIEN_model.v" \
"../../testbench/models/IOBUFDS_model.v" \