25 lines
839 B
Plaintext
25 lines
839 B
Plaintext
verilog xil_defaultlib --include "../../testbench" \
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"../../testbench/models/IDELAYCTRL_model.v" \
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"../../testbench/models/IDELAYE2_model.v" \
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"../../testbench/models/IOBUF_DCIEN_model.v" \
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"../../testbench/models/IOBUF_model.v" \
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"../../testbench/models/IOBUFDS_DCIEN_model.v" \
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"../../testbench/models/IOBUFDS_model.v" \
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"../../testbench/models/ISERDESE2_model.v" \
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"../../testbench/models/OBUFDS_model.v" \
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"../../testbench/models/ODELAYE2_model.v" \
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"../../testbench/models/OSERDESE2_model.v" \
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"../../testbench/models/OBUF_model.v" \
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"../../rtl/ddr3_controller.v" \
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"../../rtl/ddr3_phy.v" \
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"../../rtl/ddr3_top.v" \
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sv xil_defaultlib --include "../../testbench" \
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"../../testbench/ddr3.sv" \
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"../../testbench/ddr3_module.sv" \
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"../../testbench/ddr3_dimm_micron_sim.sv" \
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verilog xil_defaultlib "../../testbench/xsim/glbl.v"
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nosort
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