From cb5f78b0572113b43d38c8d9f235dca96eaa980a Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Sat, 24 May 2025 17:33:49 +0800 Subject: [PATCH] modified vivado simulation files --- testbench/xsim/file_info.txt | 22 +++++++++---------- ...sion_test.sh => regression_test_vivado.sh} | 0 testbench/xsim/vlog.prj | 11 ++++++++++ 3 files changed, 22 insertions(+), 11 deletions(-) rename testbench/xsim/{regression_test.sh => regression_test_vivado.sh} (100%) diff --git a/testbench/xsim/file_info.txt b/testbench/xsim/file_info.txt index a6e749c..f15ba49 100644 --- a/testbench/xsim/file_info.txt +++ b/testbench/xsim/file_info.txt @@ -1,14 +1,14 @@ -IDELAYCTRL_model.v,verilog,xil_defaultlib,../../testbench/IDELAYCTRL_model.v,incdir="../../testbench" -IDELAYE2_model.v,verilog,xil_defaultlib,../../testbench/IDELAYE2_model.v,incdir="../../testbench" -IOBUF_DCIEN.v,verilog,xil_defaultlib,../../testbench/IOBUF_DCIEN.v,incdir="../../testbench" -IOBUF_model.v,verilog,xil_defaultlib,../../testbench/IOBUF_model.v,incdir="../../testbench" -IOBUFDS_DCIEN_model.v,verilog,xil_defaultlib,../../testbench/IOBUFDS_DCIEN_model.v,incdir="../../testbench" -IOBUFDS_model.v,verilog,xil_defaultlib,../../testbench/IOBUFDS_model.v,incdir="../../testbench" -ISERDESE2_model.v,verilog,xil_defaultlib,../../testbench/ISERDESE2_model.v,incdir="../../testbench" -OBUFDS_model.v,verilog,xil_defaultlib,../../testbench/OBUFDS_model.v,incdir="../../testbench" -ODELAYE2_model.v,verilog,xil_defaultlib,../../testbench/ODELAYE2_model.v,incdir="../../testbench" -OSERDESE2_model.v,verilog,xil_defaultlib,../../testbench/OSERDESE2_model.v,incdir="../../testbench" -OBUF_model.v,verilog,xil_defaultlib,../../testbench/OBUF_model.v,incdir="../../testbench" +IDELAYCTRL_model.v,verilog,xil_defaultlib,../../testbench/models/IDELAYCTRL_model.v,incdir="../../testbench" +IDELAYE2_model.v,verilog,xil_defaultlib,../../testbench/models/IDELAYE2_model.v,incdir="../../testbench" +IOBUF_DCIEN.v,verilog,xil_defaultlib,../../testbench/models/IOBUF_DCIEN.v,incdir="../../testbench" +IOBUF_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUF_model.v,incdir="../../testbench" +IOBUFDS_DCIEN_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUFDS_DCIEN_model.v,incdir="../../testbench" +IOBUFDS_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUFDS_model.v,incdir="../../testbench" +ISERDESE2_model.v,verilog,xil_defaultlib,../../testbench/models/ISERDESE2_model.v,incdir="../../testbench" +OBUFDS_model.v,verilog,xil_defaultlib,../../testbench/models/OBUFDS_model.v,incdir="../../testbench" +ODELAYE2_model.v,verilog,xil_defaultlib,../../testbench/models/ODELAYE2_model.v,incdir="../../testbench" +OSERDESE2_model.v,verilog,xil_defaultlib,../../testbench/models/OSERDESE2_model.v,incdir="../../testbench" +OBUF_model.v,verilog,xil_defaultlib,../../testbench/models/OBUF_model.v,incdir="../../testbench" ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench" ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench" diff --git a/testbench/xsim/regression_test.sh b/testbench/xsim/regression_test_vivado.sh similarity index 100% rename from testbench/xsim/regression_test.sh rename to testbench/xsim/regression_test_vivado.sh diff --git a/testbench/xsim/vlog.prj b/testbench/xsim/vlog.prj index d4ee2dc..669e446 100644 --- a/testbench/xsim/vlog.prj +++ b/testbench/xsim/vlog.prj @@ -1,4 +1,15 @@ verilog xil_defaultlib --include "../../testbench" \ +"../../testbench/models/IDELAYCTRL_model.v" \ +"../../testbench/models/IDELAYE2_model.v" \ +"../../testbench/models/IOBUF_DCIEN.v" \ +"../../testbench/models/IOBUF_model.v" \ +"../../testbench/models/IOBUFDS_DCIEN_model.v" \ +"../../testbench/models/IOBUFDS_model.v" \ +"../../testbench/models/ISERDESE2_model.v" \ +"../../testbench/models/OBUFDS_model.v" \ +"../../testbench/models/ODELAYE2_model.v" \ +"../../testbench/models/OSERDESE2_model.v" \ +"../../testbench/models/OBUF_model.v" \ "../../rtl/ddr3_controller.v" \ "../../rtl/ddr3_phy.v" \ "../../rtl/ddr3_top.v" \