solve timing slack due to 64-bit counters

example_demo/enclustra_kx2_st1/ddr3_test.c

@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*
+ * helloworld.c: simple test application
+ *
+ * This application configures UART 16550 to baud rate 9600.
+ * PS7 UART (Zynq) is not initialized by this application, since
+ * bootrom/bsp configures it to baud rate 115200
+ *
+ * ------------------------------------------------
+ * | UART TYPE   BAUD RATE                        |
+ * ------------------------------------------------
+ *   uartns550   9600
+ *   uartlite    Configurable only in HW design
+ *   ps7_uart    115200 (configured by bootrom/bsp)
+ */
+#include <stdio.h>
+#include <stdint.h>
+#include "xparameters.h"
+#include "platform.h"
+#include "xil_printf.h"
+#include "xil_io.h"
+#include "sleep.h"
+
+#define DDR3_MONITOR_BASE  0x00010000
+
+#define REG_MATCH_LOW      0x00
+#define REG_MATCH_HIGH     0x04
+#define REG_MISMATCH_LOW   0x08
+#define REG_MISMATCH_HIGH  0x0C
+#define REG_TIMER_LOW      0x10
+#define REG_TIMER_HIGH     0x14
+#define REG_FAULTS         0x18
+
+#define TIMER_FREQ_HZ      100000000  // Adjust based on actual hardware clock
+
+int main()
+{
+    init_platform();
+    print("Hello World\n\r");
+    print("Successfully ran Hello World application\n\r");
+
+    while (1)  // Infinite loop
+    {
+        // Read 64-bit counters
+        uint32_t correct_lower_32 = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MATCH_LOW);
+        uint32_t correct_upper_32 = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MATCH_HIGH);
+        uint32_t wrong_lower_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MISMATCH_LOW);
+        uint32_t wrong_upper_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MISMATCH_HIGH);
+        uint32_t timer_lower_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_TIMER_LOW);
+        uint32_t timer_upper_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_TIMER_HIGH);
+        uint32_t injected_faults  = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_FAULTS);
+
+        // Combine into 64-bit values
+        long long match_count    = ((long long) correct_upper_32 << 32) | correct_lower_32;
+        long long mismatch_count = ((long long) wrong_upper_32 << 32) | wrong_lower_32;
+        long long timer_count    = ((long long) timer_upper_32 << 32) | timer_lower_32;
+
+        // Convert timer count to time in days, hours, and minutes
+        long long elapsed_seconds = timer_count / TIMER_FREQ_HZ;
+        uint32_t days    = elapsed_seconds / (24 * 3600);
+        uint32_t hours   = (elapsed_seconds % (24 * 3600)) / 3600;
+        uint32_t minutes = (elapsed_seconds % 3600) / 60;
+
+        // Print results
+        xil_printf("\n=============================\n\r");
+        xil_printf("        SYSTEM STATUS        \n\r");
+        xil_printf("=============================\n\r");
+        xil_printf(" Matched Reads   : %u M\n\r", match_count / 1000000);
+        xil_printf(" Mismatched Reads: %u \n\r", mismatch_count);
+        xil_printf(" Injected Faults : %u\n\r", injected_faults);
+        xil_printf("-----------------------------\n\r");
+        xil_printf(" Elapsed Time    : %u days, %u hours, %u minutes\n\r", days, hours, minutes);
+        xil_printf("=============================\n\r\n");
+
+
+
+        // Wait 1 second
+        usleep(1000000);
+    }
+
+    cleanup_platform();
+    return 0;  // (Will never reach here due to infinite loop)
+}

example_demo/enclustra_kx2_st1/ddr3_test.v

@@ -94,6 +94,8 @@ module ddr3_test #(
     reg[WB_ADDR_BITS-1:0] check_test_address_counter = 0; 
     reg[$clog2(WB_SEL_BITS)-1:0] write_by_byte_counter = 0;
     (* mark_debug = "true" *) reg[63:0] correct_read_data_counter = 0, wrong_read_data_counter = 0; // 64-bit counter for correct and wrong read data, this make sure the counter will not overflow when several day's worth of DDR3 test is done on hardware
+    reg increment_wrong_read_data_counter = 0;
+    reg increment_correct_read_data_counter = 0;
     (* mark_debug = "true" *) reg[WB_DATA_BITS-1:0] wrong_data, expected_data;
     reg[63:0] time_counter = 0; 
     (* mark_debug = "true" *) reg[31:0] injected_faults_counter = 0;
@@ -287,15 +289,18 @@ module ddr3_test #(
             wrong_read_data_counter <= 64'd0;
             wrong_data <= 512'd0;
             expected_data <= 512'd0;
+            increment_wrong_read_data_counter <= 0;
         end
         else begin
             if(i_calib_complete) begin          
+                increment_wrong_read_data_counter <= 1'b0;
+                increment_correct_read_data_counter <= 1'b0;
                 if ( i_wb_ack && i_aux[2:0] == 3'd3 ) begin //o_aux = 3 is for read requests from DDR3 test
                     if(i_wb_data == correct_data) begin // if read data matches the expected, increment correct_read_data_counter
-                        correct_read_data_counter <= correct_read_data_counter + 64'd1;
+                        increment_correct_read_data_counter <= 1'b1;
                     end
                     else begin
-                        wrong_read_data_counter <= wrong_read_data_counter + 64'd1;
+                        increment_wrong_read_data_counter <= 1'b1;
                         wrong_data <= i_wb_data;
                         expected_data <= correct_data;
                     end
@@ -314,6 +319,12 @@ module ddr3_test #(
                 wrong_data <= 512'd0;
                 expected_data <= 512'd0;
             end
+            if(increment_wrong_read_data_counter) begin
+                wrong_read_data_counter <= wrong_read_data_counter + 64'd1;
+            end
+            if(increment_correct_read_data_counter) begin
+                correct_read_data_counter <= correct_read_data_counter + 64'd1;
+            end
         end
 
     end
@@ -365,3 +376,4 @@ module ddr3_test #(
         .wrong_read_data_counter_0(wrong_read_data_counter)
     );
 endmodule
+