Merge pull request #14 from AngeloJacobo/vivado_ip
Added files to integrate UberDDR3 on Vivado IP Catalog
This commit is contained in:
Angelo Jacobo
GitHub
commit
93908acc94
|
|
@ -44,6 +44,11 @@ module ddr3_top_axi #(
|
||||||
parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
|
parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
|
||||||
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
|
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
|
||||||
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
|
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
|
||||||
|
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
||||||
|
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
|
||||||
|
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
|
||||||
|
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
|
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
|
parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
|
||||||
DQ_BITS = 8, //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while )
|
DQ_BITS = 8, //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while )
|
||||||
serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
|
serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
|
||||||
|
|
@ -121,12 +126,15 @@ module ddr3_top_axi #(
|
||||||
output wire[BYTE_LANES-1:0] o_ddr3_dm,
|
output wire[BYTE_LANES-1:0] o_ddr3_dm,
|
||||||
output wire o_ddr3_odt,
|
output wire o_ddr3_odt,
|
||||||
//
|
//
|
||||||
|
// Done Calibration pin
|
||||||
|
output wire o_calib_complete,
|
||||||
|
//
|
||||||
// Debug outputs
|
// Debug outputs
|
||||||
output wire[31:0] o_debug1,
|
output wire[31:0] o_debug1
|
||||||
output wire[31:0] o_debug2,
|
// output wire[31:0] o_debug2,
|
||||||
output wire[31:0] o_debug3,
|
// output wire[31:0] o_debug3,
|
||||||
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
|
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
|
||||||
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
|
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
|
||||||
);
|
);
|
||||||
|
|
||||||
wire wb_cyc;
|
wire wb_cyc;
|
||||||
|
|
@ -152,7 +160,12 @@ ddr3_top #(
|
||||||
.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 if ODELAYE2 is supported
|
.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 if ODELAYE2 is supported
|
||||||
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone for debugging is needed
|
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone for debugging is needed
|
||||||
.WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus
|
.WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus
|
||||||
.WB2_DATA_BITS(WB2_DATA_BITS) //width of 2nd wishbone data bus
|
.WB2_DATA_BITS(WB2_DATA_BITS), //width of 2nd wishbone data bus
|
||||||
|
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
||||||
|
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
|
||||||
|
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
|
||||||
|
.DIC(DIC), // Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
|
.RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
) ddr3_top_inst
|
) ddr3_top_inst
|
||||||
(
|
(
|
||||||
//clock and reset
|
//clock and reset
|
||||||
|
|
@ -205,12 +218,15 @@ ddr3_top #(
|
||||||
.o_ddr3_dm(o_ddr3_dm), // width = BYTE_LANES
|
.o_ddr3_dm(o_ddr3_dm), // width = BYTE_LANES
|
||||||
.o_ddr3_odt(o_ddr3_odt),
|
.o_ddr3_odt(o_ddr3_odt),
|
||||||
//
|
//
|
||||||
|
// Done Calibration pin
|
||||||
|
.o_calib_complete(o_calib_complete),
|
||||||
|
//
|
||||||
// Debug outputs
|
// Debug outputs
|
||||||
.o_debug1(o_debug1),
|
.o_debug1(o_debug1)
|
||||||
.o_debug2(o_debug2),
|
// .o_debug2(o_debug2),
|
||||||
.o_debug3(o_debug3),
|
// .o_debug3(o_debug3),
|
||||||
.o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
|
// .o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
|
||||||
.o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
|
// .o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
|
||||||
////////////////////////////////////
|
////////////////////////////////////
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
@ -284,4 +300,4 @@ axim2wbsp #(
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -67,6 +67,7 @@ module ddr3_controller #(
|
||||||
ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
|
ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
|
||||||
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone is needed
|
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone is needed
|
||||||
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
||||||
|
SKIP_INTERNAL_TEST = 1, // skip built-in self test (would require >2 seconds of internal test right after calibration)
|
||||||
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) (only change when you know what you are doing)
|
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) (only change when you know what you are doing)
|
||||||
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
|
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
|
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
|
||||||
|
|
@ -131,10 +132,12 @@ module ddr3_controller #(
|
||||||
output reg[LANES-1:0] o_phy_bitslip,
|
output reg[LANES-1:0] o_phy_bitslip,
|
||||||
output reg o_phy_write_leveling_calib,
|
output reg o_phy_write_leveling_calib,
|
||||||
output wire o_phy_reset,
|
output wire o_phy_reset,
|
||||||
|
// Done Calibration pin
|
||||||
|
output wire o_calib_complete,
|
||||||
// Debug port
|
// Debug port
|
||||||
output wire [31:0] o_debug1,
|
output wire [31:0] o_debug1
|
||||||
output wire [31:0] o_debug2,
|
// output wire [31:0] o_debug2,
|
||||||
output wire [31:0] o_debug3
|
// output wire [31:0] o_debug3
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -554,6 +557,7 @@ module ddr3_controller #(
|
||||||
(* mark_debug = "true" *) reg odelay_cntvalue_halfway = 0;
|
(* mark_debug = "true" *) reg odelay_cntvalue_halfway = 0;
|
||||||
reg initial_calibration_done = 0;
|
reg initial_calibration_done = 0;
|
||||||
reg final_calibration_done = 0;
|
reg final_calibration_done = 0;
|
||||||
|
assign o_calib_complete = final_calibration_done;
|
||||||
// Wishbone 2
|
// Wishbone 2
|
||||||
reg wb2_stb = 0;
|
reg wb2_stb = 0;
|
||||||
reg wb2_update = 0;
|
reg wb2_update = 0;
|
||||||
|
|
@ -2325,7 +2329,7 @@ module ddr3_controller #(
|
||||||
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
||||||
if(lane == LANES - 1) begin
|
if(lane == LANES - 1) begin
|
||||||
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
||||||
state_calibrate <= BURST_WRITE;
|
state_calibrate <= SKIP_INTERNAL_TEST? FINISH_READ : BURST_WRITE; // go straight to FINISH_READ if SKIP_INTERNAL_TEST high
|
||||||
initial_calibration_done <= 1'b1;
|
initial_calibration_done <= 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
|
|
@ -2827,11 +2831,11 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
|
||||||
end//end of always
|
end//end of always
|
||||||
// Logic connected to debug port
|
// Logic connected to debug port
|
||||||
// Logic connected to debug port
|
// Logic connected to debug port
|
||||||
wire debug_trigger;
|
// wire debug_trigger;
|
||||||
assign o_debug1 = {27'd0, state_calibrate[4:0]};
|
assign o_debug1 = {27'd0, state_calibrate[4:0]};
|
||||||
assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
|
// assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
|
||||||
assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]};
|
// assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]};
|
||||||
assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/;
|
// assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/;
|
||||||
/*********************************************************************************************************************************************/
|
/*********************************************************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -44,6 +44,7 @@ module ddr3_top #(
|
||||||
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
|
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
|
||||||
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
|
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
|
||||||
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
||||||
|
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
|
||||||
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
|
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
|
||||||
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
|
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
|
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
|
||||||
|
|
@ -104,12 +105,14 @@ module ddr3_top #(
|
||||||
output wire[BYTE_LANES-1:0] o_ddr3_dm,
|
output wire[BYTE_LANES-1:0] o_ddr3_dm,
|
||||||
output wire o_ddr3_odt, // on-die termination
|
output wire o_ddr3_odt, // on-die termination
|
||||||
//
|
//
|
||||||
|
// Done Calibration pin
|
||||||
|
output wire o_calib_complete,
|
||||||
// Debug outputs
|
// Debug outputs
|
||||||
output wire[31:0] o_debug1,
|
output wire[31:0] o_debug1
|
||||||
output wire[31:0] o_debug2,
|
// output wire[31:0] o_debug2,
|
||||||
output wire[31:0] o_debug3,
|
// output wire[31:0] o_debug3,
|
||||||
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
|
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
|
||||||
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
|
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
|
||||||
);
|
);
|
||||||
|
|
||||||
// Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
|
// Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
|
||||||
|
|
@ -182,10 +185,6 @@ ddr3_top #(
|
||||||
.o_ddr3_odt(ddr3_odt),
|
.o_ddr3_odt(ddr3_odt),
|
||||||
// Debug outputs
|
// Debug outputs
|
||||||
.o_debug1(),
|
.o_debug1(),
|
||||||
.o_debug2(),
|
|
||||||
.o_debug3(),
|
|
||||||
.o_ddr3_debug_read_dqs_p(),
|
|
||||||
.o_ddr3_debug_read_dqs_n()
|
|
||||||
////////////////////////////////////
|
////////////////////////////////////
|
||||||
);
|
);
|
||||||
*/
|
*/
|
||||||
|
|
@ -225,6 +224,7 @@ ddr3_top #(
|
||||||
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed
|
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed
|
||||||
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
|
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
|
||||||
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
|
||||||
|
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
|
||||||
.DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
|
.DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
|
||||||
.RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
|
.RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
|
||||||
) ddr3_controller_inst (
|
) ddr3_controller_inst (
|
||||||
|
|
@ -278,10 +278,12 @@ ddr3_top #(
|
||||||
.o_phy_bitslip(bitslip),
|
.o_phy_bitslip(bitslip),
|
||||||
.o_phy_write_leveling_calib(write_leveling_calib),
|
.o_phy_write_leveling_calib(write_leveling_calib),
|
||||||
.o_phy_reset(reset),
|
.o_phy_reset(reset),
|
||||||
|
// Done Calibration pin
|
||||||
|
.o_calib_complete(o_calib_complete),
|
||||||
// Debug outputs
|
// Debug outputs
|
||||||
.o_debug1(o_debug1),
|
.o_debug1(o_debug1)
|
||||||
.o_debug2(o_debug2),
|
// .o_debug2(o_debug2),
|
||||||
.o_debug3(o_debug3)
|
// .o_debug3(o_debug3)
|
||||||
);
|
);
|
||||||
|
|
||||||
ddr3_phy #(
|
ddr3_phy #(
|
||||||
|
|
@ -336,8 +338,8 @@ ddr3_top #(
|
||||||
.io_ddr3_dqs_n(io_ddr3_dqs_n),
|
.io_ddr3_dqs_n(io_ddr3_dqs_n),
|
||||||
.o_ddr3_dm(o_ddr3_dm),
|
.o_ddr3_dm(o_ddr3_dm),
|
||||||
.o_ddr3_odt(o_ddr3_odt), // on-die termination
|
.o_ddr3_odt(o_ddr3_odt), // on-die termination
|
||||||
.o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
|
.o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
|
||||||
.o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
|
.o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
|
||||||
);
|
);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
||||||
|
# This file is automatically written. Do not modify.
|
||||||
|
proc gen_USERPARAMETER_DDR3_CLK_PERIOD_VALUE {CONTROLLER_CLK_PERIOD } {expr $CONTROLLER_CLK_PERIOD / 4}
|
||||||
|
proc gen_USERPARAMETER_wb_addr_bits_VALUE {ROW_BITS COL_BITS BA_BITS } {expr $ROW_BITS + $COL_BITS + $BA_BITS - 3}
|
||||||
|
proc gen_USERPARAMETER_wb_data_bits_VALUE {DQ_BITS BYTE_LANES } {expr $DQ_BITS * $BYTE_LANES * 8}
|
||||||
|
proc gen_USERPARAMETER_wb_sel_bits_VALUE {wb_data_bits } {expr $wb_data_bits / 8}
|
||||||
|
proc gen_USERPARAMETER_wb2_sel_bits_VALUE {WB2_DATA_BITS } {expr $WB2_DATA_BITS / 8}
|
||||||
|
proc gen_USERPARAMETER_cmd_len_VALUE {BA_BITS ROW_BITS } {expr 4 + 3 + $BA_BITS + $ROW_BITS}
|
||||||
|
proc gen_USERPARAMETER_AXI_LSBS_VALUE {wb_data_bits } {expr (log( $wb_data_bits )/log(2)) - 3}
|
||||||
|
proc gen_USERPARAMETER_AXI_ADDR_WIDTH_VALUE {wb_addr_bits AXI_LSBS } {expr $wb_addr_bits + $AXI_LSBS}
|
||||||
|
proc gen_USERPARAMETER_AXI_DATA_WIDTH_VALUE {wb_data_bits } {expr $wb_data_bits}
|
||||||
|
|
@ -0,0 +1,415 @@
|
||||||
|
# Definitional proc to organize widgets for parameters.
|
||||||
|
proc init_gui { IPINST } {
|
||||||
|
ipgui::add_param $IPINST -name "Component_Name"
|
||||||
|
#Adding Page
|
||||||
|
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||||
|
ipgui::add_param $IPINST -name "AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "AXI_ID_WIDTH" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "AXI_LSBS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "BA_BITS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "BYTE_LANES" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "COL_BITS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "CONTROLLER_CLK_PERIOD" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "DDR3_CLK_PERIOD" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "DIC" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "DQ_BITS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "ECC_ENABLE" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "MICRON_SIM" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "ODELAY_SUPPORTED" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "ROW_BITS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "RTT_NOM" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "SECOND_WISHBONE" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "SKIP_INTERNAL_TEST" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "WB2_ADDR_BITS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "WB2_DATA_BITS" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "WB_ERROR" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "cmd_len" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "serdes_ratio" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "wb2_sel_bits" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "wb_addr_bits" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "wb_data_bits" -parent ${Page_0}
|
||||||
|
ipgui::add_param $IPINST -name "wb_sel_bits" -parent ${Page_0}
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } {
|
||||||
|
# Procedure called to update AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } {
|
||||||
|
# Procedure called to validate AXI_ADDR_WIDTH
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||||
|
# Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||||
|
# Procedure called to validate AXI_DATA_WIDTH
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } {
|
||||||
|
# Procedure called to update AXI_ID_WIDTH when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } {
|
||||||
|
# Procedure called to validate AXI_ID_WIDTH
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS } {
|
||||||
|
# Procedure called to update AXI_LSBS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS } {
|
||||||
|
# Procedure called to validate AXI_LSBS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to update BA_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to validate BA_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to update BYTE_LANES when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to validate BYTE_LANES
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } {
|
||||||
|
# Procedure called to update COL_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } {
|
||||||
|
# Procedure called to validate COL_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to update CONTROLLER_CLK_PERIOD when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to validate CONTROLLER_CLK_PERIOD
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD } {
|
||||||
|
# Procedure called to update DDR3_CLK_PERIOD when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD } {
|
||||||
|
# Procedure called to validate DDR3_CLK_PERIOD
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.DIC { PARAM_VALUE.DIC } {
|
||||||
|
# Procedure called to update DIC when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.DIC { PARAM_VALUE.DIC } {
|
||||||
|
# Procedure called to validate DIC
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } {
|
||||||
|
# Procedure called to update DQ_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } {
|
||||||
|
# Procedure called to validate DQ_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } {
|
||||||
|
# Procedure called to update ECC_ENABLE when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } {
|
||||||
|
# Procedure called to validate ECC_ENABLE
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } {
|
||||||
|
# Procedure called to update MICRON_SIM when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } {
|
||||||
|
# Procedure called to validate MICRON_SIM
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } {
|
||||||
|
# Procedure called to update ODELAY_SUPPORTED when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } {
|
||||||
|
# Procedure called to validate ODELAY_SUPPORTED
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to update ROW_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to validate ROW_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } {
|
||||||
|
# Procedure called to update RTT_NOM when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } {
|
||||||
|
# Procedure called to validate RTT_NOM
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } {
|
||||||
|
# Procedure called to update SECOND_WISHBONE when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } {
|
||||||
|
# Procedure called to validate SECOND_WISHBONE
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } {
|
||||||
|
# Procedure called to update SKIP_INTERNAL_TEST when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } {
|
||||||
|
# Procedure called to validate SKIP_INTERNAL_TEST
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } {
|
||||||
|
# Procedure called to update WB2_ADDR_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } {
|
||||||
|
# Procedure called to validate WB2_ADDR_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to update WB2_DATA_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to validate WB2_DATA_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } {
|
||||||
|
# Procedure called to update WB_ERROR when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } {
|
||||||
|
# Procedure called to validate WB_ERROR
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len } {
|
||||||
|
# Procedure called to update cmd_len when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len } {
|
||||||
|
# Procedure called to validate cmd_len
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } {
|
||||||
|
# Procedure called to update serdes_ratio when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } {
|
||||||
|
# Procedure called to validate serdes_ratio
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits } {
|
||||||
|
# Procedure called to update wb2_sel_bits when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits } {
|
||||||
|
# Procedure called to validate wb2_sel_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits } {
|
||||||
|
# Procedure called to update wb_addr_bits when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits } {
|
||||||
|
# Procedure called to validate wb_addr_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to update wb_data_bits when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to validate wb_data_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits } {
|
||||||
|
# Procedure called to update wb_sel_bits when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits } {
|
||||||
|
# Procedure called to validate wb_sel_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD { MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.CONTROLLER_CLK_PERIOD}] ${MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.DDR3_CLK_PERIOD { MODELPARAM_VALUE.DDR3_CLK_PERIOD PARAM_VALUE.DDR3_CLK_PERIOD } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.DDR3_CLK_PERIOD}] ${MODELPARAM_VALUE.DDR3_CLK_PERIOD}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.ROW_BITS { MODELPARAM_VALUE.ROW_BITS PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.ROW_BITS}] ${MODELPARAM_VALUE.ROW_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.COL_BITS { MODELPARAM_VALUE.COL_BITS PARAM_VALUE.COL_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.COL_BITS}] ${MODELPARAM_VALUE.COL_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.BA_BITS { MODELPARAM_VALUE.BA_BITS PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.BA_BITS}] ${MODELPARAM_VALUE.BA_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.BYTE_LANES { MODELPARAM_VALUE.BYTE_LANES PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.BYTE_LANES}] ${MODELPARAM_VALUE.BYTE_LANES}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_ID_WIDTH { MODELPARAM_VALUE.AXI_ID_WIDTH PARAM_VALUE.AXI_ID_WIDTH } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH}] ${MODELPARAM_VALUE.AXI_ID_WIDTH}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.WB2_ADDR_BITS { MODELPARAM_VALUE.WB2_ADDR_BITS PARAM_VALUE.WB2_ADDR_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.WB2_ADDR_BITS}] ${MODELPARAM_VALUE.WB2_ADDR_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.WB2_DATA_BITS { MODELPARAM_VALUE.WB2_DATA_BITS PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.WB2_DATA_BITS}] ${MODELPARAM_VALUE.WB2_DATA_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.MICRON_SIM { MODELPARAM_VALUE.MICRON_SIM PARAM_VALUE.MICRON_SIM } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.MICRON_SIM}] ${MODELPARAM_VALUE.MICRON_SIM}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.ODELAY_SUPPORTED { MODELPARAM_VALUE.ODELAY_SUPPORTED PARAM_VALUE.ODELAY_SUPPORTED } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.ODELAY_SUPPORTED}] ${MODELPARAM_VALUE.ODELAY_SUPPORTED}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.SECOND_WISHBONE { MODELPARAM_VALUE.SECOND_WISHBONE PARAM_VALUE.SECOND_WISHBONE } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.SECOND_WISHBONE}] ${MODELPARAM_VALUE.SECOND_WISHBONE}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.WB_ERROR { MODELPARAM_VALUE.WB_ERROR PARAM_VALUE.WB_ERROR } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.WB_ERROR}] ${MODELPARAM_VALUE.WB_ERROR}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.SKIP_INTERNAL_TEST { MODELPARAM_VALUE.SKIP_INTERNAL_TEST PARAM_VALUE.SKIP_INTERNAL_TEST } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.SKIP_INTERNAL_TEST}] ${MODELPARAM_VALUE.SKIP_INTERNAL_TEST}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.ECC_ENABLE { MODELPARAM_VALUE.ECC_ENABLE PARAM_VALUE.ECC_ENABLE } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.ECC_ENABLE}] ${MODELPARAM_VALUE.ECC_ENABLE}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.DIC { MODELPARAM_VALUE.DIC PARAM_VALUE.DIC } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.DIC}] ${MODELPARAM_VALUE.DIC}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.RTT_NOM { MODELPARAM_VALUE.RTT_NOM PARAM_VALUE.RTT_NOM } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.RTT_NOM}] ${MODELPARAM_VALUE.RTT_NOM}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.DQ_BITS { MODELPARAM_VALUE.DQ_BITS PARAM_VALUE.DQ_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.DQ_BITS}] ${MODELPARAM_VALUE.DQ_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.serdes_ratio { MODELPARAM_VALUE.serdes_ratio PARAM_VALUE.serdes_ratio } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.serdes_ratio}] ${MODELPARAM_VALUE.serdes_ratio}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb_addr_bits { MODELPARAM_VALUE.wb_addr_bits PARAM_VALUE.wb_addr_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb_addr_bits}] ${MODELPARAM_VALUE.wb_addr_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb_data_bits { MODELPARAM_VALUE.wb_data_bits PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb_data_bits}] ${MODELPARAM_VALUE.wb_data_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb_sel_bits { MODELPARAM_VALUE.wb_sel_bits PARAM_VALUE.wb_sel_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb_sel_bits}] ${MODELPARAM_VALUE.wb_sel_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb2_sel_bits { MODELPARAM_VALUE.wb2_sel_bits PARAM_VALUE.wb2_sel_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb2_sel_bits}] ${MODELPARAM_VALUE.wb2_sel_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.cmd_len { MODELPARAM_VALUE.cmd_len PARAM_VALUE.cmd_len } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.cmd_len}] ${MODELPARAM_VALUE.cmd_len}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_LSBS { MODELPARAM_VALUE.AXI_LSBS PARAM_VALUE.AXI_LSBS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_LSBS}] ${MODELPARAM_VALUE.AXI_LSBS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_ADDR_WIDTH { MODELPARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.AXI_ADDR_WIDTH } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXI_ADDR_WIDTH}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,467 @@
|
||||||
|
|
||||||
|
# Loading additional proc with user specified bodies to compute parameter values.
|
||||||
|
source [file join [file dirname [file dirname [info script]]] gui/uberddr3_axi_v1_0.gtcl]
|
||||||
|
|
||||||
|
# Definitional proc to organize widgets for parameters.
|
||||||
|
proc init_gui { IPINST } {
|
||||||
|
ipgui::add_param $IPINST -name "Component_Name"
|
||||||
|
#Adding Page
|
||||||
|
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||||
|
set CONTROLLER_CLK_PERIOD [ipgui::add_param $IPINST -name "CONTROLLER_CLK_PERIOD" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Clock period of the controller interface in picoseconds} ${CONTROLLER_CLK_PERIOD}
|
||||||
|
set DDR3_CLK_PERIOD [ipgui::add_param $IPINST -name "DDR3_CLK_PERIOD" -parent ${Page_0}]
|
||||||
|
set_property tooltip {1/4 of Controller Clock Period} ${DDR3_CLK_PERIOD}
|
||||||
|
set ROW_BITS [ipgui::add_param $IPINST -name "ROW_BITS" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Width of row address} ${ROW_BITS}
|
||||||
|
set COL_BITS [ipgui::add_param $IPINST -name "COL_BITS" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Width of column address} ${COL_BITS}
|
||||||
|
set BA_BITS [ipgui::add_param $IPINST -name "BA_BITS" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Width of bank address} ${BA_BITS}
|
||||||
|
set BYTE_LANES [ipgui::add_param $IPINST -name "BYTE_LANES" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Number of byte lanes of DDR3 RAM in the FPGA board (e.g. x16 DDR3 will have 2 byte lanes)} ${BYTE_LANES}
|
||||||
|
set ECC_ENABLE [ipgui::add_param $IPINST -name "ECC_ENABLE" -parent ${Page_0}]
|
||||||
|
set_property tooltip {0 = DIsabled, 1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC} ${ECC_ENABLE}
|
||||||
|
set SKIP_INTERNAL_TEST [ipgui::add_param $IPINST -name "SKIP_INTERNAL_TEST" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Check to skip built-in self-test (check this if UberDDR3 will be connected to Microblaze)} ${SKIP_INTERNAL_TEST}
|
||||||
|
set ODELAY_SUPPORTED [ipgui::add_param $IPINST -name "ODELAY_SUPPORTED" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Check if FPGA supports ODELAYE2 primitive (e.g. FPGA with HP banks like Kintex-7)} ${ODELAY_SUPPORTED}
|
||||||
|
set MICRON_SIM [ipgui::add_param $IPINST -name "MICRON_SIM" -parent ${Page_0}]
|
||||||
|
set_property tooltip {Check if design will be run on simulation to shorten calibration} ${MICRON_SIM}
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.wb_addr_bits PARAM_VALUE.AXI_LSBS } {
|
||||||
|
# Procedure called to update AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set AXI_ADDR_WIDTH ${PARAM_VALUE.AXI_ADDR_WIDTH}
|
||||||
|
set wb_addr_bits ${PARAM_VALUE.wb_addr_bits}
|
||||||
|
set AXI_LSBS ${PARAM_VALUE.AXI_LSBS}
|
||||||
|
set values(wb_addr_bits) [get_property value $wb_addr_bits]
|
||||||
|
set values(AXI_LSBS) [get_property value $AXI_LSBS]
|
||||||
|
set_property value [gen_USERPARAMETER_AXI_ADDR_WIDTH_VALUE $values(wb_addr_bits) $values(AXI_LSBS)] $AXI_ADDR_WIDTH
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } {
|
||||||
|
# Procedure called to validate AXI_ADDR_WIDTH
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set AXI_DATA_WIDTH ${PARAM_VALUE.AXI_DATA_WIDTH}
|
||||||
|
set wb_data_bits ${PARAM_VALUE.wb_data_bits}
|
||||||
|
set values(wb_data_bits) [get_property value $wb_data_bits]
|
||||||
|
set_property value [gen_USERPARAMETER_AXI_DATA_WIDTH_VALUE $values(wb_data_bits)] $AXI_DATA_WIDTH
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||||
|
# Procedure called to validate AXI_DATA_WIDTH
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to update AXI_LSBS when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set AXI_LSBS ${PARAM_VALUE.AXI_LSBS}
|
||||||
|
set wb_data_bits ${PARAM_VALUE.wb_data_bits}
|
||||||
|
set values(wb_data_bits) [get_property value $wb_data_bits]
|
||||||
|
set_property value [gen_USERPARAMETER_AXI_LSBS_VALUE $values(wb_data_bits)] $AXI_LSBS
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS } {
|
||||||
|
# Procedure called to validate AXI_LSBS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to update DDR3_CLK_PERIOD when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set DDR3_CLK_PERIOD ${PARAM_VALUE.DDR3_CLK_PERIOD}
|
||||||
|
set CONTROLLER_CLK_PERIOD ${PARAM_VALUE.CONTROLLER_CLK_PERIOD}
|
||||||
|
set values(CONTROLLER_CLK_PERIOD) [get_property value $CONTROLLER_CLK_PERIOD]
|
||||||
|
set_property value [gen_USERPARAMETER_DDR3_CLK_PERIOD_VALUE $values(CONTROLLER_CLK_PERIOD)] $DDR3_CLK_PERIOD
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD } {
|
||||||
|
# Procedure called to validate DDR3_CLK_PERIOD
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len PARAM_VALUE.BA_BITS PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to update cmd_len when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set cmd_len ${PARAM_VALUE.cmd_len}
|
||||||
|
set BA_BITS ${PARAM_VALUE.BA_BITS}
|
||||||
|
set ROW_BITS ${PARAM_VALUE.ROW_BITS}
|
||||||
|
set values(BA_BITS) [get_property value $BA_BITS]
|
||||||
|
set values(ROW_BITS) [get_property value $ROW_BITS]
|
||||||
|
set_property value [gen_USERPARAMETER_cmd_len_VALUE $values(BA_BITS) $values(ROW_BITS)] $cmd_len
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len } {
|
||||||
|
# Procedure called to validate cmd_len
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to update wb2_sel_bits when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set wb2_sel_bits ${PARAM_VALUE.wb2_sel_bits}
|
||||||
|
set WB2_DATA_BITS ${PARAM_VALUE.WB2_DATA_BITS}
|
||||||
|
set values(WB2_DATA_BITS) [get_property value $WB2_DATA_BITS]
|
||||||
|
set_property value [gen_USERPARAMETER_wb2_sel_bits_VALUE $values(WB2_DATA_BITS)] $wb2_sel_bits
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits } {
|
||||||
|
# Procedure called to validate wb2_sel_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits PARAM_VALUE.ROW_BITS PARAM_VALUE.COL_BITS PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to update wb_addr_bits when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set wb_addr_bits ${PARAM_VALUE.wb_addr_bits}
|
||||||
|
set ROW_BITS ${PARAM_VALUE.ROW_BITS}
|
||||||
|
set COL_BITS ${PARAM_VALUE.COL_BITS}
|
||||||
|
set BA_BITS ${PARAM_VALUE.BA_BITS}
|
||||||
|
set values(ROW_BITS) [get_property value $ROW_BITS]
|
||||||
|
set values(COL_BITS) [get_property value $COL_BITS]
|
||||||
|
set values(BA_BITS) [get_property value $BA_BITS]
|
||||||
|
set_property value [gen_USERPARAMETER_wb_addr_bits_VALUE $values(ROW_BITS) $values(COL_BITS) $values(BA_BITS)] $wb_addr_bits
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits } {
|
||||||
|
# Procedure called to validate wb_addr_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits PARAM_VALUE.DQ_BITS PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to update wb_data_bits when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set wb_data_bits ${PARAM_VALUE.wb_data_bits}
|
||||||
|
set DQ_BITS ${PARAM_VALUE.DQ_BITS}
|
||||||
|
set BYTE_LANES ${PARAM_VALUE.BYTE_LANES}
|
||||||
|
set values(DQ_BITS) [get_property value $DQ_BITS]
|
||||||
|
set values(BYTE_LANES) [get_property value $BYTE_LANES]
|
||||||
|
set_property value [gen_USERPARAMETER_wb_data_bits_VALUE $values(DQ_BITS) $values(BYTE_LANES)] $wb_data_bits
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to validate wb_data_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to update wb_sel_bits when any of the dependent parameters in the arguments change
|
||||||
|
|
||||||
|
set wb_sel_bits ${PARAM_VALUE.wb_sel_bits}
|
||||||
|
set wb_data_bits ${PARAM_VALUE.wb_data_bits}
|
||||||
|
set values(wb_data_bits) [get_property value $wb_data_bits]
|
||||||
|
set_property value [gen_USERPARAMETER_wb_sel_bits_VALUE $values(wb_data_bits)] $wb_sel_bits
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits } {
|
||||||
|
# Procedure called to validate wb_sel_bits
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } {
|
||||||
|
# Procedure called to update AXI_ID_WIDTH when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } {
|
||||||
|
# Procedure called to validate AXI_ID_WIDTH
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to update BA_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to validate BA_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to update BYTE_LANES when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to validate BYTE_LANES
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } {
|
||||||
|
# Procedure called to update COL_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } {
|
||||||
|
# Procedure called to validate COL_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to update CONTROLLER_CLK_PERIOD when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to validate CONTROLLER_CLK_PERIOD
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.DIC { PARAM_VALUE.DIC } {
|
||||||
|
# Procedure called to update DIC when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.DIC { PARAM_VALUE.DIC } {
|
||||||
|
# Procedure called to validate DIC
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } {
|
||||||
|
# Procedure called to update DQ_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } {
|
||||||
|
# Procedure called to validate DQ_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } {
|
||||||
|
# Procedure called to update ECC_ENABLE when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } {
|
||||||
|
# Procedure called to validate ECC_ENABLE
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } {
|
||||||
|
# Procedure called to update MICRON_SIM when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } {
|
||||||
|
# Procedure called to validate MICRON_SIM
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } {
|
||||||
|
# Procedure called to update ODELAY_SUPPORTED when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } {
|
||||||
|
# Procedure called to validate ODELAY_SUPPORTED
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to update ROW_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to validate ROW_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } {
|
||||||
|
# Procedure called to update RTT_NOM when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } {
|
||||||
|
# Procedure called to validate RTT_NOM
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } {
|
||||||
|
# Procedure called to update SECOND_WISHBONE when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } {
|
||||||
|
# Procedure called to validate SECOND_WISHBONE
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } {
|
||||||
|
# Procedure called to update SKIP_INTERNAL_TEST when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } {
|
||||||
|
# Procedure called to validate SKIP_INTERNAL_TEST
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } {
|
||||||
|
# Procedure called to update WB2_ADDR_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } {
|
||||||
|
# Procedure called to validate WB2_ADDR_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to update WB2_DATA_BITS when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to validate WB2_DATA_BITS
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } {
|
||||||
|
# Procedure called to update WB_ERROR when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } {
|
||||||
|
# Procedure called to validate WB_ERROR
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } {
|
||||||
|
# Procedure called to update serdes_ratio when any of the dependent parameters in the arguments change
|
||||||
|
}
|
||||||
|
|
||||||
|
proc validate_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } {
|
||||||
|
# Procedure called to validate serdes_ratio
|
||||||
|
return true
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD { MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD PARAM_VALUE.CONTROLLER_CLK_PERIOD } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.CONTROLLER_CLK_PERIOD}] ${MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.DDR3_CLK_PERIOD { MODELPARAM_VALUE.DDR3_CLK_PERIOD PARAM_VALUE.DDR3_CLK_PERIOD } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.DDR3_CLK_PERIOD}] ${MODELPARAM_VALUE.DDR3_CLK_PERIOD}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.ROW_BITS { MODELPARAM_VALUE.ROW_BITS PARAM_VALUE.ROW_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.ROW_BITS}] ${MODELPARAM_VALUE.ROW_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.COL_BITS { MODELPARAM_VALUE.COL_BITS PARAM_VALUE.COL_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.COL_BITS}] ${MODELPARAM_VALUE.COL_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.BA_BITS { MODELPARAM_VALUE.BA_BITS PARAM_VALUE.BA_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.BA_BITS}] ${MODELPARAM_VALUE.BA_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.BYTE_LANES { MODELPARAM_VALUE.BYTE_LANES PARAM_VALUE.BYTE_LANES } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.BYTE_LANES}] ${MODELPARAM_VALUE.BYTE_LANES}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_ID_WIDTH { MODELPARAM_VALUE.AXI_ID_WIDTH PARAM_VALUE.AXI_ID_WIDTH } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH}] ${MODELPARAM_VALUE.AXI_ID_WIDTH}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.WB2_ADDR_BITS { MODELPARAM_VALUE.WB2_ADDR_BITS PARAM_VALUE.WB2_ADDR_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.WB2_ADDR_BITS}] ${MODELPARAM_VALUE.WB2_ADDR_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.WB2_DATA_BITS { MODELPARAM_VALUE.WB2_DATA_BITS PARAM_VALUE.WB2_DATA_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.WB2_DATA_BITS}] ${MODELPARAM_VALUE.WB2_DATA_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.MICRON_SIM { MODELPARAM_VALUE.MICRON_SIM PARAM_VALUE.MICRON_SIM } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.MICRON_SIM}] ${MODELPARAM_VALUE.MICRON_SIM}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.ODELAY_SUPPORTED { MODELPARAM_VALUE.ODELAY_SUPPORTED PARAM_VALUE.ODELAY_SUPPORTED } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.ODELAY_SUPPORTED}] ${MODELPARAM_VALUE.ODELAY_SUPPORTED}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.SECOND_WISHBONE { MODELPARAM_VALUE.SECOND_WISHBONE PARAM_VALUE.SECOND_WISHBONE } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.SECOND_WISHBONE}] ${MODELPARAM_VALUE.SECOND_WISHBONE}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.WB_ERROR { MODELPARAM_VALUE.WB_ERROR PARAM_VALUE.WB_ERROR } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.WB_ERROR}] ${MODELPARAM_VALUE.WB_ERROR}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.SKIP_INTERNAL_TEST { MODELPARAM_VALUE.SKIP_INTERNAL_TEST PARAM_VALUE.SKIP_INTERNAL_TEST } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.SKIP_INTERNAL_TEST}] ${MODELPARAM_VALUE.SKIP_INTERNAL_TEST}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.ECC_ENABLE { MODELPARAM_VALUE.ECC_ENABLE PARAM_VALUE.ECC_ENABLE } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.ECC_ENABLE}] ${MODELPARAM_VALUE.ECC_ENABLE}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.DIC { MODELPARAM_VALUE.DIC PARAM_VALUE.DIC } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.DIC}] ${MODELPARAM_VALUE.DIC}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.RTT_NOM { MODELPARAM_VALUE.RTT_NOM PARAM_VALUE.RTT_NOM } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.RTT_NOM}] ${MODELPARAM_VALUE.RTT_NOM}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.DQ_BITS { MODELPARAM_VALUE.DQ_BITS PARAM_VALUE.DQ_BITS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.DQ_BITS}] ${MODELPARAM_VALUE.DQ_BITS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.serdes_ratio { MODELPARAM_VALUE.serdes_ratio PARAM_VALUE.serdes_ratio } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.serdes_ratio}] ${MODELPARAM_VALUE.serdes_ratio}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb_addr_bits { MODELPARAM_VALUE.wb_addr_bits PARAM_VALUE.wb_addr_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb_addr_bits}] ${MODELPARAM_VALUE.wb_addr_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb_data_bits { MODELPARAM_VALUE.wb_data_bits PARAM_VALUE.wb_data_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb_data_bits}] ${MODELPARAM_VALUE.wb_data_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb_sel_bits { MODELPARAM_VALUE.wb_sel_bits PARAM_VALUE.wb_sel_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb_sel_bits}] ${MODELPARAM_VALUE.wb_sel_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.wb2_sel_bits { MODELPARAM_VALUE.wb2_sel_bits PARAM_VALUE.wb2_sel_bits } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.wb2_sel_bits}] ${MODELPARAM_VALUE.wb2_sel_bits}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.cmd_len { MODELPARAM_VALUE.cmd_len PARAM_VALUE.cmd_len } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.cmd_len}] ${MODELPARAM_VALUE.cmd_len}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_LSBS { MODELPARAM_VALUE.AXI_LSBS PARAM_VALUE.AXI_LSBS } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_LSBS}] ${MODELPARAM_VALUE.AXI_LSBS}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_ADDR_WIDTH { MODELPARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.AXI_ADDR_WIDTH } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXI_ADDR_WIDTH}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } {
|
||||||
|
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||||
|
set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH}
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Reference in New Issue