diff --git a/rtl/axi/ddr3_top_axi.v b/rtl/axi/ddr3_top_axi.v index 323a3d7..e5ab389 100644 --- a/rtl/axi/ddr3_top_axi.v +++ b/rtl/axi/ddr3_top_axi.v @@ -44,6 +44,11 @@ module ddr3_top_axi #( parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW) ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed + WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error) + SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration) + parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) + parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing) + parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing) parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration DQ_BITS = 8, //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while ) serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4) @@ -121,12 +126,15 @@ module ddr3_top_axi #( output wire[BYTE_LANES-1:0] o_ddr3_dm, output wire o_ddr3_odt, // + // Done Calibration pin + output wire o_calib_complete, + // // Debug outputs - output wire[31:0] o_debug1, - output wire[31:0] o_debug2, - output wire[31:0] o_debug3, - output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p, - output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n + output wire[31:0] o_debug1 +// output wire[31:0] o_debug2, +// output wire[31:0] o_debug3, +// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p, +// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n ); wire wb_cyc; @@ -152,7 +160,12 @@ ddr3_top #( .ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 if ODELAYE2 is supported .SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone for debugging is needed .WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus - .WB2_DATA_BITS(WB2_DATA_BITS) //width of 2nd wishbone data bus + .WB2_DATA_BITS(WB2_DATA_BITS), //width of 2nd wishbone data bus + .WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error) + .SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration) + .ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) + .DIC(DIC), // Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing) + .RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing) ) ddr3_top_inst ( //clock and reset @@ -205,12 +218,15 @@ ddr3_top #( .o_ddr3_dm(o_ddr3_dm), // width = BYTE_LANES .o_ddr3_odt(o_ddr3_odt), // + // Done Calibration pin + .o_calib_complete(o_calib_complete), + // // Debug outputs - .o_debug1(o_debug1), - .o_debug2(o_debug2), - .o_debug3(o_debug3), - .o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p), - .o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n) + .o_debug1(o_debug1) + // .o_debug2(o_debug2), + // .o_debug3(o_debug3), + // .o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p), + // .o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n) //////////////////////////////////// ); @@ -284,4 +300,4 @@ axim2wbsp #( endmodule - \ No newline at end of file + diff --git a/rtl/ddr3_controller.v b/rtl/ddr3_controller.v index 925af22..3f86357 100644 --- a/rtl/ddr3_controller.v +++ b/rtl/ddr3_controller.v @@ -67,6 +67,7 @@ module ddr3_controller #( ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone is needed WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error) + SKIP_INTERNAL_TEST = 1, // skip built-in self test (would require >2 seconds of internal test right after calibration) parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) (only change when you know what you are doing) parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing) parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) @@ -131,10 +132,12 @@ module ddr3_controller #( output reg[LANES-1:0] o_phy_bitslip, output reg o_phy_write_leveling_calib, output wire o_phy_reset, + // Done Calibration pin + output wire o_calib_complete, // Debug port - output wire [31:0] o_debug1, - output wire [31:0] o_debug2, - output wire [31:0] o_debug3 + output wire [31:0] o_debug1 +// output wire [31:0] o_debug2, +// output wire [31:0] o_debug3 ); @@ -554,6 +557,7 @@ module ddr3_controller #( (* mark_debug = "true" *) reg odelay_cntvalue_halfway = 0; reg initial_calibration_done = 0; reg final_calibration_done = 0; + assign o_calib_complete = final_calibration_done; // Wishbone 2 reg wb2_stb = 0; reg wb2_update = 0; @@ -2325,7 +2329,7 @@ module ddr3_controller #( /* verilator lint_off WIDTH */ if(lane == LANES - 1) begin /* verilator lint_on WIDTH */ - state_calibrate <= BURST_WRITE; + state_calibrate <= SKIP_INTERNAL_TEST? FINISH_READ : BURST_WRITE; // go straight to FINISH_READ if SKIP_INTERNAL_TEST high initial_calibration_done <= 1'b1; end else begin @@ -2827,11 +2831,11 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin end//end of always // Logic connected to debug port // Logic connected to debug port - wire debug_trigger; +// wire debug_trigger; assign o_debug1 = {27'd0, state_calibrate[4:0]}; - assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]}; - assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]}; - assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/; +// assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]}; +// assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]}; +// assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/; /*********************************************************************************************************************************************/ diff --git a/rtl/ddr3_top.v b/rtl/ddr3_top.v index b367218..cf9a651 100644 --- a/rtl/ddr3_top.v +++ b/rtl/ddr3_top.v @@ -44,6 +44,7 @@ module ddr3_top #( ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error) + SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration) parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing) parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing) @@ -104,12 +105,14 @@ module ddr3_top #( output wire[BYTE_LANES-1:0] o_ddr3_dm, output wire o_ddr3_odt, // on-die termination // + // Done Calibration pin + output wire o_calib_complete, // Debug outputs - output wire[31:0] o_debug1, - output wire[31:0] o_debug2, - output wire[31:0] o_debug3, - output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p, - output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n + output wire[31:0] o_debug1 +// output wire[31:0] o_debug2, +// output wire[31:0] o_debug3, +// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p, +// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n ); // Instantiation Template (DEFAULT VALUE IS FOR ARTY S7) @@ -182,10 +185,6 @@ ddr3_top #( .o_ddr3_odt(ddr3_odt), // Debug outputs .o_debug1(), - .o_debug2(), - .o_debug3(), - .o_ddr3_debug_read_dqs_p(), - .o_ddr3_debug_read_dqs_n() //////////////////////////////////// ); */ @@ -225,6 +224,7 @@ ddr3_top #( .SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed .ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) .WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error) + .SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration) .DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) .RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) ) ddr3_controller_inst ( @@ -278,10 +278,12 @@ ddr3_top #( .o_phy_bitslip(bitslip), .o_phy_write_leveling_calib(write_leveling_calib), .o_phy_reset(reset), + // Done Calibration pin + .o_calib_complete(o_calib_complete), // Debug outputs - .o_debug1(o_debug1), - .o_debug2(o_debug2), - .o_debug3(o_debug3) + .o_debug1(o_debug1) +// .o_debug2(o_debug2), +// .o_debug3(o_debug3) ); ddr3_phy #( @@ -336,8 +338,8 @@ ddr3_top #( .io_ddr3_dqs_n(io_ddr3_dqs_n), .o_ddr3_dm(o_ddr3_dm), .o_ddr3_odt(o_ddr3_odt), // on-die termination - .o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p), - .o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n) + .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/), + .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/) ); endmodule diff --git a/vivado_custom_ip/component.xml b/vivado_custom_ip/component.xml new file mode 100644 index 0000000..adfc16f --- /dev/null +++ b/vivado_custom_ip/component.xml @@ -0,0 +1,2109 @@ + + + OpenIPHub + DDR3_Memory_Controller + uberddr3_axi + 1.0 + + + s_axi + + + + + + + + + AWID + + + s_axi_awid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWLEN + + + s_axi_awlen + + + + + AWSIZE + + + s_axi_awsize + + + + + AWBURST + + + s_axi_awburst + + + + + AWLOCK + + + s_axi_awlock + + + + + AWCACHE + + + s_axi_awcache + + + + + AWPROT + + + s_axi_awprot + + + + + AWQOS + + + s_axi_awqos + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WLAST + + + s_axi_wlast + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BID + + + s_axi_bid + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARID + + + s_axi_arid + + + + + ARADDR + + + s_axi_araddr + + + + + ARLEN + + + s_axi_arlen + + + + + ARSIZE + + + s_axi_arsize + + + + + ARBURST + + + s_axi_arburst + + + + + ARLOCK + + + s_axi_arlock + + + + + ARCACHE + + + s_axi_arcache + + + + + ARPROT + + + s_axi_arprot + + + + + ARQOS + + + s_axi_arqos + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RID + + + s_axi_rid + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RLAST + + + s_axi_rlast + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + i_rst_n + + + + + + + RST + + + i_rst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + i_controller_clk + + + + + + + CLK + + + i_controller_clk + + + + + + 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s_axi_arqos + + in + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rid + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 127 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_clk_p + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_clk_n + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_reset_n + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_cke + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_cs_n + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_ras_n + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_cas_n + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_we_n + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_addr + + out + + 13 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_ba_addr + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + io_ddr3_dq + + inout + + 15 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + io_ddr3_dqs + + inout + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + io_ddr3_dqs_n + + inout + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_dm + + out + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_ddr3_odt + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_calib_complete + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + o_debug1 + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + CONTROLLER_CLK_PERIOD + Controller Clk Period + 12000 + + + DDR3_CLK_PERIOD + Ddr3 Clk Period + 3000 + + + ROW_BITS + Row Bits + 14 + + + COL_BITS + Col Bits + 10 + + + BA_BITS + Ba Bits + 3 + + + BYTE_LANES + Byte Lanes + 2 + + + AXI_ID_WIDTH + Axi Id Width + 4 + + + WB2_ADDR_BITS + Wb2 Addr Bits + 7 + + + WB2_DATA_BITS + Wb2 Data Bits + 32 + + + MICRON_SIM + Micron Sim + false + + + ODELAY_SUPPORTED + Odelay Supported + false + + + SECOND_WISHBONE + Second Wishbone + false + + + WB_ERROR + Wb Error + 0 + + + SKIP_INTERNAL_TEST + Skip Internal Test + false + + + ECC_ENABLE + Ecc Enable + 0 + + + DIC + Dic + "00" + + + RTT_NOM + Rtt Nom + "011" + + + DQ_BITS + Dq Bits + 8 + + + serdes_ratio + Serdes Ratio + 4 + + + wb_addr_bits + Wb Addr Bits + 24 + + + wb_data_bits + Wb Data Bits + 128 + + + wb_sel_bits + Wb Sel Bits + 16 + + + wb2_sel_bits + Wb2 Sel Bits + 4 + + + cmd_len + Cmd Len + 24 + + + AXI_LSBS + Axi Lsbs + 4 + + + AXI_ADDR_WIDTH + Axi Addr Width + 28 + + + AXI_DATA_WIDTH + Axi Data Width + 128 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../rtl/axi/axi_addr.v + verilogSource + + + ../rtl/axi/axim2wbsp.v + verilogSource + + + ../rtl/axi/aximrd2wbsp.v + verilogSource + + + ../rtl/axi/aximwr2wbsp.v + verilogSource + + + ../rtl/ddr3_controller.v + verilogSource + + + ../rtl/ddr3_phy.v + verilogSource + + + ../rtl/ddr3_top.v + verilogSource + + + ../rtl/axi/sfifo.v + verilogSource + + + ../rtl/axi/skidbuffer.v + verilogSource + + + ../rtl/axi/wbarbiter.v + verilogSource + + + ../rtl/ecc/ecc_dec.sv + systemVerilogSource + + + ../rtl/ecc/ecc_enc.sv + systemVerilogSource + + + ../rtl/axi/ddr3_top_axi.v + verilogSource + CHECKSUM_4123fcc3 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../rtl/axi/axi_addr.v + verilogSource + + + ../rtl/axi/axim2wbsp.v + verilogSource + + + ../rtl/axi/aximrd2wbsp.v + verilogSource + + + ../rtl/axi/aximwr2wbsp.v + verilogSource + + + ../rtl/ddr3_controller.v + verilogSource + + + ../rtl/ddr3_phy.v + verilogSource + + + ../rtl/ddr3_top.v + verilogSource + + + ../rtl/axi/sfifo.v + verilogSource + + + ../rtl/axi/skidbuffer.v + verilogSource + + + ../rtl/axi/wbarbiter.v + verilogSource + + + ../rtl/ecc/ecc_dec.sv + systemVerilogSource + + + ../rtl/ecc/ecc_enc.sv + systemVerilogSource + + + ../rtl/axi/ddr3_top_axi.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/uberddr3_axi_v1_0.tcl + tclSource + CHECKSUM_30e22270 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + gui/uberddr3_axi_v1_0.gtcl + GTCL + + + + UberDDR3 is an open-source DDR3 memory controller designed for Xilinx FPGAs. It features a 4:1 memory interface with customizable parameters, allowing seamless integration with a wide range of DDR3 memory devices. The user interface is AXI4-compliant + + + CONTROLLER_CLK_PERIOD + Controller Clock Period (ps) + 12000 + + + DDR3_CLK_PERIOD + DDR3 Clock Period (ps) + 3000 + + + + false + + + + + + ROW_BITS + Row Bits + 14 + + + COL_BITS + Column Bits + 10 + + + BA_BITS + Bank Bits + 3 + + + BYTE_LANES + Byte Lanes + 2 + + + AXI_ID_WIDTH + Axi Id Width + 4 + + + WB2_ADDR_BITS + Wb2 Addr Bits + 7 + + + WB2_DATA_BITS + Wb2 Data Bits + 32 + + + MICRON_SIM + Micron Simulation + false + + + ODELAY_SUPPORTED + ODELAY Supported + false + + + SECOND_WISHBONE + Second Wishbone + false + + + WB_ERROR + Wb Error + 0 + + + SKIP_INTERNAL_TEST + Skip Internal Test + false + + + ECC_ENABLE + ECC Enable + 0 + + + DIC + Dic + "00" + + + RTT_NOM + Rtt Nom + "011" + + + DQ_BITS + Dq Bits + 8 + + + serdes_ratio + Serdes Ratio + 4 + + + wb_addr_bits + Wb Addr Bits + 24 + + + + false + + + + + + wb_data_bits + Wb Data Bits + 128 + + + + false + + + + + + wb_sel_bits + Wb Sel Bits + 16 + + + + false + + + + + + wb2_sel_bits + Wb2 Sel Bits + 4 + + + + false + + + + + + cmd_len + Cmd Len + 24 + + + + false + + + + + + AXI_LSBS + Axi Lsbs + 4 + + + + false + + + + + + AXI_ADDR_WIDTH + Axi Addr Width + 28 + + + + false + + + + + + AXI_DATA_WIDTH + Axi Data Width + 128 + + + + false + + + + + + Component_Name + uberddr3_axi_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + kintexu + + + /UserIP + + uberddr3_axi_v1_0 + package_project + https://github.com/AngeloJacobo/UberDDR3 + 9 + 2024-10-19T05:33:11Z + + + + + + 2022.1 + + + + + + + + + diff --git a/vivado_custom_ip/gui/uberddr3_axi_v1_0.gtcl b/vivado_custom_ip/gui/uberddr3_axi_v1_0.gtcl new file mode 100644 index 0000000..901fbfc --- /dev/null +++ b/vivado_custom_ip/gui/uberddr3_axi_v1_0.gtcl @@ -0,0 +1,10 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DDR3_CLK_PERIOD_VALUE {CONTROLLER_CLK_PERIOD } {expr $CONTROLLER_CLK_PERIOD / 4} +proc gen_USERPARAMETER_wb_addr_bits_VALUE {ROW_BITS COL_BITS BA_BITS } {expr $ROW_BITS + $COL_BITS + $BA_BITS - 3} +proc gen_USERPARAMETER_wb_data_bits_VALUE {DQ_BITS BYTE_LANES } {expr $DQ_BITS * $BYTE_LANES * 8} +proc gen_USERPARAMETER_wb_sel_bits_VALUE {wb_data_bits } {expr $wb_data_bits / 8} +proc gen_USERPARAMETER_wb2_sel_bits_VALUE {WB2_DATA_BITS } {expr $WB2_DATA_BITS / 8} +proc gen_USERPARAMETER_cmd_len_VALUE {BA_BITS ROW_BITS } {expr 4 + 3 + $BA_BITS + $ROW_BITS} +proc gen_USERPARAMETER_AXI_LSBS_VALUE {wb_data_bits } {expr (log( $wb_data_bits )/log(2)) - 3} +proc gen_USERPARAMETER_AXI_ADDR_WIDTH_VALUE {wb_addr_bits AXI_LSBS } {expr $wb_addr_bits + $AXI_LSBS} +proc gen_USERPARAMETER_AXI_DATA_WIDTH_VALUE {wb_data_bits } {expr $wb_data_bits} diff --git a/vivado_custom_ip/xgui/ddr3_top_axi_v1_0.tcl b/vivado_custom_ip/xgui/ddr3_top_axi_v1_0.tcl new file mode 100644 index 0000000..a462c49 --- /dev/null +++ b/vivado_custom_ip/xgui/ddr3_top_axi_v1_0.tcl @@ -0,0 +1,415 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_ID_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_LSBS" -parent ${Page_0} + ipgui::add_param $IPINST -name "BA_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "BYTE_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "COL_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "CONTROLLER_CLK_PERIOD" -parent ${Page_0} + ipgui::add_param $IPINST -name "DDR3_CLK_PERIOD" -parent ${Page_0} + ipgui::add_param $IPINST -name "DIC" -parent ${Page_0} + ipgui::add_param $IPINST -name "DQ_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "ECC_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "MICRON_SIM" -parent ${Page_0} + ipgui::add_param $IPINST -name "ODELAY_SUPPORTED" -parent ${Page_0} + ipgui::add_param $IPINST -name "ROW_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "RTT_NOM" -parent ${Page_0} + ipgui::add_param $IPINST -name "SECOND_WISHBONE" -parent ${Page_0} + ipgui::add_param $IPINST -name "SKIP_INTERNAL_TEST" -parent ${Page_0} + ipgui::add_param $IPINST -name "WB2_ADDR_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "WB2_DATA_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "WB_ERROR" -parent ${Page_0} + ipgui::add_param $IPINST -name "cmd_len" -parent ${Page_0} + ipgui::add_param $IPINST -name "serdes_ratio" -parent ${Page_0} + ipgui::add_param $IPINST -name "wb2_sel_bits" -parent ${Page_0} + ipgui::add_param $IPINST -name "wb_addr_bits" -parent ${Page_0} + ipgui::add_param $IPINST -name "wb_data_bits" -parent ${Page_0} + ipgui::add_param $IPINST -name "wb_sel_bits" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to update AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to validate AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to validate AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to update AXI_ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to validate AXI_ID_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS } { + # Procedure called to update AXI_LSBS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS } { + # Procedure called to validate AXI_LSBS + return true +} + +proc update_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } { + # Procedure called to update BA_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } { + # Procedure called to validate BA_BITS + return true +} + +proc update_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } { + # Procedure called to update BYTE_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } { + # Procedure called to validate BYTE_LANES + return true +} + +proc update_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } { + # Procedure called to update COL_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } { + # Procedure called to validate COL_BITS + return true +} + +proc update_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to update CONTROLLER_CLK_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to validate CONTROLLER_CLK_PERIOD + return true +} + +proc update_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD } { + # Procedure called to update DDR3_CLK_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD } { + # Procedure called to validate DDR3_CLK_PERIOD + return true +} + +proc update_PARAM_VALUE.DIC { PARAM_VALUE.DIC } { + # Procedure called to update DIC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIC { PARAM_VALUE.DIC } { + # Procedure called to validate DIC + return true +} + +proc update_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } { + # Procedure called to update DQ_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } { + # Procedure called to validate DQ_BITS + return true +} + +proc update_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } { + # Procedure called to update ECC_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } { + # Procedure called to validate ECC_ENABLE + return true +} + +proc update_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } { + # Procedure called to update MICRON_SIM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } { + # Procedure called to validate MICRON_SIM + return true +} + +proc update_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } { + # Procedure called to update ODELAY_SUPPORTED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } { + # Procedure called to validate ODELAY_SUPPORTED + return true +} + +proc update_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } { + # Procedure called to update ROW_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } { + # Procedure called to validate ROW_BITS + return true +} + +proc update_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } { + # Procedure called to update RTT_NOM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } { + # Procedure called to validate RTT_NOM + return true +} + +proc update_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } { + # Procedure called to update SECOND_WISHBONE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } { + # Procedure called to validate SECOND_WISHBONE + return true +} + +proc update_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } { + # Procedure called to update SKIP_INTERNAL_TEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } { + # Procedure called to validate SKIP_INTERNAL_TEST + return true +} + +proc update_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } { + # Procedure called to update WB2_ADDR_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } { + # Procedure called to validate WB2_ADDR_BITS + return true +} + +proc update_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to update WB2_DATA_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to validate WB2_DATA_BITS + return true +} + +proc update_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } { + # Procedure called to update WB_ERROR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } { + # Procedure called to validate WB_ERROR + return true +} + +proc update_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len } { + # Procedure called to update cmd_len when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len } { + # Procedure called to validate cmd_len + return true +} + +proc update_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } { + # Procedure called to update serdes_ratio when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } { + # Procedure called to validate serdes_ratio + return true +} + +proc update_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits } { + # Procedure called to update wb2_sel_bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits } { + # Procedure called to validate wb2_sel_bits + return true +} + +proc update_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits } { + # Procedure called to update wb_addr_bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits } { + # Procedure called to validate wb_addr_bits + return true +} + +proc update_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits } { + # Procedure called to update wb_data_bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits } { + # Procedure called to validate wb_data_bits + return true +} + +proc update_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits } { + # Procedure called to update wb_sel_bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits } { + # Procedure called to validate wb_sel_bits + return true +} + + +proc update_MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD { MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CONTROLLER_CLK_PERIOD}] ${MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD} +} + +proc update_MODELPARAM_VALUE.DDR3_CLK_PERIOD { MODELPARAM_VALUE.DDR3_CLK_PERIOD PARAM_VALUE.DDR3_CLK_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDR3_CLK_PERIOD}] ${MODELPARAM_VALUE.DDR3_CLK_PERIOD} +} + +proc update_MODELPARAM_VALUE.ROW_BITS { MODELPARAM_VALUE.ROW_BITS PARAM_VALUE.ROW_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ROW_BITS}] ${MODELPARAM_VALUE.ROW_BITS} +} + +proc update_MODELPARAM_VALUE.COL_BITS { MODELPARAM_VALUE.COL_BITS PARAM_VALUE.COL_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.COL_BITS}] ${MODELPARAM_VALUE.COL_BITS} +} + +proc update_MODELPARAM_VALUE.BA_BITS { MODELPARAM_VALUE.BA_BITS PARAM_VALUE.BA_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BA_BITS}] ${MODELPARAM_VALUE.BA_BITS} +} + +proc update_MODELPARAM_VALUE.BYTE_LANES { MODELPARAM_VALUE.BYTE_LANES PARAM_VALUE.BYTE_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BYTE_LANES}] ${MODELPARAM_VALUE.BYTE_LANES} +} + +proc update_MODELPARAM_VALUE.AXI_ID_WIDTH { MODELPARAM_VALUE.AXI_ID_WIDTH PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH}] ${MODELPARAM_VALUE.AXI_ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.WB2_ADDR_BITS { MODELPARAM_VALUE.WB2_ADDR_BITS PARAM_VALUE.WB2_ADDR_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WB2_ADDR_BITS}] ${MODELPARAM_VALUE.WB2_ADDR_BITS} +} + +proc update_MODELPARAM_VALUE.WB2_DATA_BITS { MODELPARAM_VALUE.WB2_DATA_BITS PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WB2_DATA_BITS}] ${MODELPARAM_VALUE.WB2_DATA_BITS} +} + +proc update_MODELPARAM_VALUE.MICRON_SIM { MODELPARAM_VALUE.MICRON_SIM PARAM_VALUE.MICRON_SIM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MICRON_SIM}] ${MODELPARAM_VALUE.MICRON_SIM} +} + +proc update_MODELPARAM_VALUE.ODELAY_SUPPORTED { MODELPARAM_VALUE.ODELAY_SUPPORTED PARAM_VALUE.ODELAY_SUPPORTED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ODELAY_SUPPORTED}] ${MODELPARAM_VALUE.ODELAY_SUPPORTED} +} + +proc update_MODELPARAM_VALUE.SECOND_WISHBONE { MODELPARAM_VALUE.SECOND_WISHBONE PARAM_VALUE.SECOND_WISHBONE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SECOND_WISHBONE}] ${MODELPARAM_VALUE.SECOND_WISHBONE} +} + +proc update_MODELPARAM_VALUE.WB_ERROR { MODELPARAM_VALUE.WB_ERROR PARAM_VALUE.WB_ERROR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WB_ERROR}] ${MODELPARAM_VALUE.WB_ERROR} +} + +proc update_MODELPARAM_VALUE.SKIP_INTERNAL_TEST { MODELPARAM_VALUE.SKIP_INTERNAL_TEST PARAM_VALUE.SKIP_INTERNAL_TEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SKIP_INTERNAL_TEST}] ${MODELPARAM_VALUE.SKIP_INTERNAL_TEST} +} + +proc update_MODELPARAM_VALUE.ECC_ENABLE { MODELPARAM_VALUE.ECC_ENABLE PARAM_VALUE.ECC_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ECC_ENABLE}] ${MODELPARAM_VALUE.ECC_ENABLE} +} + +proc update_MODELPARAM_VALUE.DIC { MODELPARAM_VALUE.DIC PARAM_VALUE.DIC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIC}] ${MODELPARAM_VALUE.DIC} +} + +proc update_MODELPARAM_VALUE.RTT_NOM { MODELPARAM_VALUE.RTT_NOM PARAM_VALUE.RTT_NOM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RTT_NOM}] ${MODELPARAM_VALUE.RTT_NOM} +} + +proc update_MODELPARAM_VALUE.DQ_BITS { MODELPARAM_VALUE.DQ_BITS PARAM_VALUE.DQ_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DQ_BITS}] ${MODELPARAM_VALUE.DQ_BITS} +} + +proc update_MODELPARAM_VALUE.serdes_ratio { MODELPARAM_VALUE.serdes_ratio PARAM_VALUE.serdes_ratio } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.serdes_ratio}] ${MODELPARAM_VALUE.serdes_ratio} +} + +proc update_MODELPARAM_VALUE.wb_addr_bits { MODELPARAM_VALUE.wb_addr_bits PARAM_VALUE.wb_addr_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb_addr_bits}] ${MODELPARAM_VALUE.wb_addr_bits} +} + +proc update_MODELPARAM_VALUE.wb_data_bits { MODELPARAM_VALUE.wb_data_bits PARAM_VALUE.wb_data_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb_data_bits}] ${MODELPARAM_VALUE.wb_data_bits} +} + +proc update_MODELPARAM_VALUE.wb_sel_bits { MODELPARAM_VALUE.wb_sel_bits PARAM_VALUE.wb_sel_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb_sel_bits}] ${MODELPARAM_VALUE.wb_sel_bits} +} + +proc update_MODELPARAM_VALUE.wb2_sel_bits { MODELPARAM_VALUE.wb2_sel_bits PARAM_VALUE.wb2_sel_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb2_sel_bits}] ${MODELPARAM_VALUE.wb2_sel_bits} +} + +proc update_MODELPARAM_VALUE.cmd_len { MODELPARAM_VALUE.cmd_len PARAM_VALUE.cmd_len } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.cmd_len}] ${MODELPARAM_VALUE.cmd_len} +} + +proc update_MODELPARAM_VALUE.AXI_LSBS { MODELPARAM_VALUE.AXI_LSBS PARAM_VALUE.AXI_LSBS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_LSBS}] ${MODELPARAM_VALUE.AXI_LSBS} +} + +proc update_MODELPARAM_VALUE.AXI_ADDR_WIDTH { MODELPARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH} +} + diff --git a/vivado_custom_ip/xgui/uberddr3_axi_v1_0.tcl b/vivado_custom_ip/xgui/uberddr3_axi_v1_0.tcl new file mode 100644 index 0000000..e20ff24 --- /dev/null +++ b/vivado_custom_ip/xgui/uberddr3_axi_v1_0.tcl @@ -0,0 +1,467 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/uberddr3_axi_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set CONTROLLER_CLK_PERIOD [ipgui::add_param $IPINST -name "CONTROLLER_CLK_PERIOD" -parent ${Page_0}] + set_property tooltip {Clock period of the controller interface in picoseconds} ${CONTROLLER_CLK_PERIOD} + set DDR3_CLK_PERIOD [ipgui::add_param $IPINST -name "DDR3_CLK_PERIOD" -parent ${Page_0}] + set_property tooltip {1/4 of Controller Clock Period} ${DDR3_CLK_PERIOD} + set ROW_BITS [ipgui::add_param $IPINST -name "ROW_BITS" -parent ${Page_0}] + set_property tooltip {Width of row address} ${ROW_BITS} + set COL_BITS [ipgui::add_param $IPINST -name "COL_BITS" -parent ${Page_0}] + set_property tooltip {Width of column address} ${COL_BITS} + set BA_BITS [ipgui::add_param $IPINST -name "BA_BITS" -parent ${Page_0}] + set_property tooltip {Width of bank address} ${BA_BITS} + set BYTE_LANES [ipgui::add_param $IPINST -name "BYTE_LANES" -parent ${Page_0}] + set_property tooltip {Number of byte lanes of DDR3 RAM in the FPGA board (e.g. x16 DDR3 will have 2 byte lanes)} ${BYTE_LANES} + set ECC_ENABLE [ipgui::add_param $IPINST -name "ECC_ENABLE" -parent ${Page_0}] + set_property tooltip {0 = DIsabled, 1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC} ${ECC_ENABLE} + set SKIP_INTERNAL_TEST [ipgui::add_param $IPINST -name "SKIP_INTERNAL_TEST" -parent ${Page_0}] + set_property tooltip {Check to skip built-in self-test (check this if UberDDR3 will be connected to Microblaze)} ${SKIP_INTERNAL_TEST} + set ODELAY_SUPPORTED [ipgui::add_param $IPINST -name "ODELAY_SUPPORTED" -parent ${Page_0}] + set_property tooltip {Check if FPGA supports ODELAYE2 primitive (e.g. FPGA with HP banks like Kintex-7)} ${ODELAY_SUPPORTED} + set MICRON_SIM [ipgui::add_param $IPINST -name "MICRON_SIM" -parent ${Page_0}] + set_property tooltip {Check if design will be run on simulation to shorten calibration} ${MICRON_SIM} + + +} + +proc update_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.wb_addr_bits PARAM_VALUE.AXI_LSBS } { + # Procedure called to update AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change + + set AXI_ADDR_WIDTH ${PARAM_VALUE.AXI_ADDR_WIDTH} + set wb_addr_bits ${PARAM_VALUE.wb_addr_bits} + set AXI_LSBS ${PARAM_VALUE.AXI_LSBS} + set values(wb_addr_bits) [get_property value $wb_addr_bits] + set values(AXI_LSBS) [get_property value $AXI_LSBS] + set_property value [gen_USERPARAMETER_AXI_ADDR_WIDTH_VALUE $values(wb_addr_bits) $values(AXI_LSBS)] $AXI_ADDR_WIDTH +} + +proc validate_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to validate AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.wb_data_bits } { + # Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change + + set AXI_DATA_WIDTH ${PARAM_VALUE.AXI_DATA_WIDTH} + set wb_data_bits ${PARAM_VALUE.wb_data_bits} + set values(wb_data_bits) [get_property value $wb_data_bits] + set_property value [gen_USERPARAMETER_AXI_DATA_WIDTH_VALUE $values(wb_data_bits)] $AXI_DATA_WIDTH +} + +proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to validate AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS PARAM_VALUE.wb_data_bits } { + # Procedure called to update AXI_LSBS when any of the dependent parameters in the arguments change + + set AXI_LSBS ${PARAM_VALUE.AXI_LSBS} + set wb_data_bits ${PARAM_VALUE.wb_data_bits} + set values(wb_data_bits) [get_property value $wb_data_bits] + set_property value [gen_USERPARAMETER_AXI_LSBS_VALUE $values(wb_data_bits)] $AXI_LSBS +} + +proc validate_PARAM_VALUE.AXI_LSBS { PARAM_VALUE.AXI_LSBS } { + # Procedure called to validate AXI_LSBS + return true +} + +proc update_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to update DDR3_CLK_PERIOD when any of the dependent parameters in the arguments change + + set DDR3_CLK_PERIOD ${PARAM_VALUE.DDR3_CLK_PERIOD} + set CONTROLLER_CLK_PERIOD ${PARAM_VALUE.CONTROLLER_CLK_PERIOD} + set values(CONTROLLER_CLK_PERIOD) [get_property value $CONTROLLER_CLK_PERIOD] + set_property value [gen_USERPARAMETER_DDR3_CLK_PERIOD_VALUE $values(CONTROLLER_CLK_PERIOD)] $DDR3_CLK_PERIOD +} + +proc validate_PARAM_VALUE.DDR3_CLK_PERIOD { PARAM_VALUE.DDR3_CLK_PERIOD } { + # Procedure called to validate DDR3_CLK_PERIOD + return true +} + +proc update_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len PARAM_VALUE.BA_BITS PARAM_VALUE.ROW_BITS } { + # Procedure called to update cmd_len when any of the dependent parameters in the arguments change + + set cmd_len ${PARAM_VALUE.cmd_len} + set BA_BITS ${PARAM_VALUE.BA_BITS} + set ROW_BITS ${PARAM_VALUE.ROW_BITS} + set values(BA_BITS) [get_property value $BA_BITS] + set values(ROW_BITS) [get_property value $ROW_BITS] + set_property value [gen_USERPARAMETER_cmd_len_VALUE $values(BA_BITS) $values(ROW_BITS)] $cmd_len +} + +proc validate_PARAM_VALUE.cmd_len { PARAM_VALUE.cmd_len } { + # Procedure called to validate cmd_len + return true +} + +proc update_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to update wb2_sel_bits when any of the dependent parameters in the arguments change + + set wb2_sel_bits ${PARAM_VALUE.wb2_sel_bits} + set WB2_DATA_BITS ${PARAM_VALUE.WB2_DATA_BITS} + set values(WB2_DATA_BITS) [get_property value $WB2_DATA_BITS] + set_property value [gen_USERPARAMETER_wb2_sel_bits_VALUE $values(WB2_DATA_BITS)] $wb2_sel_bits +} + +proc validate_PARAM_VALUE.wb2_sel_bits { PARAM_VALUE.wb2_sel_bits } { + # Procedure called to validate wb2_sel_bits + return true +} + +proc update_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits PARAM_VALUE.ROW_BITS PARAM_VALUE.COL_BITS PARAM_VALUE.BA_BITS } { + # Procedure called to update wb_addr_bits when any of the dependent parameters in the arguments change + + set wb_addr_bits ${PARAM_VALUE.wb_addr_bits} + set ROW_BITS ${PARAM_VALUE.ROW_BITS} + set COL_BITS ${PARAM_VALUE.COL_BITS} + set BA_BITS ${PARAM_VALUE.BA_BITS} + set values(ROW_BITS) [get_property value $ROW_BITS] + set values(COL_BITS) [get_property value $COL_BITS] + set values(BA_BITS) [get_property value $BA_BITS] + set_property value [gen_USERPARAMETER_wb_addr_bits_VALUE $values(ROW_BITS) $values(COL_BITS) $values(BA_BITS)] $wb_addr_bits +} + +proc validate_PARAM_VALUE.wb_addr_bits { PARAM_VALUE.wb_addr_bits } { + # Procedure called to validate wb_addr_bits + return true +} + +proc update_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits PARAM_VALUE.DQ_BITS PARAM_VALUE.BYTE_LANES } { + # Procedure called to update wb_data_bits when any of the dependent parameters in the arguments change + + set wb_data_bits ${PARAM_VALUE.wb_data_bits} + set DQ_BITS ${PARAM_VALUE.DQ_BITS} + set BYTE_LANES ${PARAM_VALUE.BYTE_LANES} + set values(DQ_BITS) [get_property value $DQ_BITS] + set values(BYTE_LANES) [get_property value $BYTE_LANES] + set_property value [gen_USERPARAMETER_wb_data_bits_VALUE $values(DQ_BITS) $values(BYTE_LANES)] $wb_data_bits +} + +proc validate_PARAM_VALUE.wb_data_bits { PARAM_VALUE.wb_data_bits } { + # Procedure called to validate wb_data_bits + return true +} + +proc update_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits PARAM_VALUE.wb_data_bits } { + # Procedure called to update wb_sel_bits when any of the dependent parameters in the arguments change + + set wb_sel_bits ${PARAM_VALUE.wb_sel_bits} + set wb_data_bits ${PARAM_VALUE.wb_data_bits} + set values(wb_data_bits) [get_property value $wb_data_bits] + set_property value [gen_USERPARAMETER_wb_sel_bits_VALUE $values(wb_data_bits)] $wb_sel_bits +} + +proc validate_PARAM_VALUE.wb_sel_bits { PARAM_VALUE.wb_sel_bits } { + # Procedure called to validate wb_sel_bits + return true +} + +proc update_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to update AXI_ID_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ID_WIDTH { PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to validate AXI_ID_WIDTH + return true +} + +proc update_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } { + # Procedure called to update BA_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BA_BITS { PARAM_VALUE.BA_BITS } { + # Procedure called to validate BA_BITS + return true +} + +proc update_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } { + # Procedure called to update BYTE_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BYTE_LANES { PARAM_VALUE.BYTE_LANES } { + # Procedure called to validate BYTE_LANES + return true +} + +proc update_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } { + # Procedure called to update COL_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.COL_BITS { PARAM_VALUE.COL_BITS } { + # Procedure called to validate COL_BITS + return true +} + +proc update_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to update CONTROLLER_CLK_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CONTROLLER_CLK_PERIOD { PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to validate CONTROLLER_CLK_PERIOD + return true +} + +proc update_PARAM_VALUE.DIC { PARAM_VALUE.DIC } { + # Procedure called to update DIC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIC { PARAM_VALUE.DIC } { + # Procedure called to validate DIC + return true +} + +proc update_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } { + # Procedure called to update DQ_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DQ_BITS { PARAM_VALUE.DQ_BITS } { + # Procedure called to validate DQ_BITS + return true +} + +proc update_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } { + # Procedure called to update ECC_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ECC_ENABLE { PARAM_VALUE.ECC_ENABLE } { + # Procedure called to validate ECC_ENABLE + return true +} + +proc update_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } { + # Procedure called to update MICRON_SIM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MICRON_SIM { PARAM_VALUE.MICRON_SIM } { + # Procedure called to validate MICRON_SIM + return true +} + +proc update_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } { + # Procedure called to update ODELAY_SUPPORTED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ODELAY_SUPPORTED { PARAM_VALUE.ODELAY_SUPPORTED } { + # Procedure called to validate ODELAY_SUPPORTED + return true +} + +proc update_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } { + # Procedure called to update ROW_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ROW_BITS { PARAM_VALUE.ROW_BITS } { + # Procedure called to validate ROW_BITS + return true +} + +proc update_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } { + # Procedure called to update RTT_NOM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RTT_NOM { PARAM_VALUE.RTT_NOM } { + # Procedure called to validate RTT_NOM + return true +} + +proc update_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } { + # Procedure called to update SECOND_WISHBONE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SECOND_WISHBONE { PARAM_VALUE.SECOND_WISHBONE } { + # Procedure called to validate SECOND_WISHBONE + return true +} + +proc update_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } { + # Procedure called to update SKIP_INTERNAL_TEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SKIP_INTERNAL_TEST { PARAM_VALUE.SKIP_INTERNAL_TEST } { + # Procedure called to validate SKIP_INTERNAL_TEST + return true +} + +proc update_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } { + # Procedure called to update WB2_ADDR_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WB2_ADDR_BITS { PARAM_VALUE.WB2_ADDR_BITS } { + # Procedure called to validate WB2_ADDR_BITS + return true +} + +proc update_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to update WB2_DATA_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WB2_DATA_BITS { PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to validate WB2_DATA_BITS + return true +} + +proc update_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } { + # Procedure called to update WB_ERROR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WB_ERROR { PARAM_VALUE.WB_ERROR } { + # Procedure called to validate WB_ERROR + return true +} + +proc update_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } { + # Procedure called to update serdes_ratio when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.serdes_ratio { PARAM_VALUE.serdes_ratio } { + # Procedure called to validate serdes_ratio + return true +} + + +proc update_MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD { MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD PARAM_VALUE.CONTROLLER_CLK_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CONTROLLER_CLK_PERIOD}] ${MODELPARAM_VALUE.CONTROLLER_CLK_PERIOD} +} + +proc update_MODELPARAM_VALUE.DDR3_CLK_PERIOD { MODELPARAM_VALUE.DDR3_CLK_PERIOD PARAM_VALUE.DDR3_CLK_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDR3_CLK_PERIOD}] ${MODELPARAM_VALUE.DDR3_CLK_PERIOD} +} + +proc update_MODELPARAM_VALUE.ROW_BITS { MODELPARAM_VALUE.ROW_BITS PARAM_VALUE.ROW_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ROW_BITS}] ${MODELPARAM_VALUE.ROW_BITS} +} + +proc update_MODELPARAM_VALUE.COL_BITS { MODELPARAM_VALUE.COL_BITS PARAM_VALUE.COL_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.COL_BITS}] ${MODELPARAM_VALUE.COL_BITS} +} + +proc update_MODELPARAM_VALUE.BA_BITS { MODELPARAM_VALUE.BA_BITS PARAM_VALUE.BA_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BA_BITS}] ${MODELPARAM_VALUE.BA_BITS} +} + +proc update_MODELPARAM_VALUE.BYTE_LANES { MODELPARAM_VALUE.BYTE_LANES PARAM_VALUE.BYTE_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BYTE_LANES}] ${MODELPARAM_VALUE.BYTE_LANES} +} + +proc update_MODELPARAM_VALUE.AXI_ID_WIDTH { MODELPARAM_VALUE.AXI_ID_WIDTH PARAM_VALUE.AXI_ID_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH}] ${MODELPARAM_VALUE.AXI_ID_WIDTH} +} + +proc update_MODELPARAM_VALUE.WB2_ADDR_BITS { MODELPARAM_VALUE.WB2_ADDR_BITS PARAM_VALUE.WB2_ADDR_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WB2_ADDR_BITS}] ${MODELPARAM_VALUE.WB2_ADDR_BITS} +} + +proc update_MODELPARAM_VALUE.WB2_DATA_BITS { MODELPARAM_VALUE.WB2_DATA_BITS PARAM_VALUE.WB2_DATA_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WB2_DATA_BITS}] ${MODELPARAM_VALUE.WB2_DATA_BITS} +} + +proc update_MODELPARAM_VALUE.MICRON_SIM { MODELPARAM_VALUE.MICRON_SIM PARAM_VALUE.MICRON_SIM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MICRON_SIM}] ${MODELPARAM_VALUE.MICRON_SIM} +} + +proc update_MODELPARAM_VALUE.ODELAY_SUPPORTED { MODELPARAM_VALUE.ODELAY_SUPPORTED PARAM_VALUE.ODELAY_SUPPORTED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ODELAY_SUPPORTED}] ${MODELPARAM_VALUE.ODELAY_SUPPORTED} +} + +proc update_MODELPARAM_VALUE.SECOND_WISHBONE { MODELPARAM_VALUE.SECOND_WISHBONE PARAM_VALUE.SECOND_WISHBONE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SECOND_WISHBONE}] ${MODELPARAM_VALUE.SECOND_WISHBONE} +} + +proc update_MODELPARAM_VALUE.WB_ERROR { MODELPARAM_VALUE.WB_ERROR PARAM_VALUE.WB_ERROR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WB_ERROR}] ${MODELPARAM_VALUE.WB_ERROR} +} + +proc update_MODELPARAM_VALUE.SKIP_INTERNAL_TEST { MODELPARAM_VALUE.SKIP_INTERNAL_TEST PARAM_VALUE.SKIP_INTERNAL_TEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SKIP_INTERNAL_TEST}] ${MODELPARAM_VALUE.SKIP_INTERNAL_TEST} +} + +proc update_MODELPARAM_VALUE.ECC_ENABLE { MODELPARAM_VALUE.ECC_ENABLE PARAM_VALUE.ECC_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ECC_ENABLE}] ${MODELPARAM_VALUE.ECC_ENABLE} +} + +proc update_MODELPARAM_VALUE.DIC { MODELPARAM_VALUE.DIC PARAM_VALUE.DIC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIC}] ${MODELPARAM_VALUE.DIC} +} + +proc update_MODELPARAM_VALUE.RTT_NOM { MODELPARAM_VALUE.RTT_NOM PARAM_VALUE.RTT_NOM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RTT_NOM}] ${MODELPARAM_VALUE.RTT_NOM} +} + +proc update_MODELPARAM_VALUE.DQ_BITS { MODELPARAM_VALUE.DQ_BITS PARAM_VALUE.DQ_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DQ_BITS}] ${MODELPARAM_VALUE.DQ_BITS} +} + +proc update_MODELPARAM_VALUE.serdes_ratio { MODELPARAM_VALUE.serdes_ratio PARAM_VALUE.serdes_ratio } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.serdes_ratio}] ${MODELPARAM_VALUE.serdes_ratio} +} + +proc update_MODELPARAM_VALUE.wb_addr_bits { MODELPARAM_VALUE.wb_addr_bits PARAM_VALUE.wb_addr_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb_addr_bits}] ${MODELPARAM_VALUE.wb_addr_bits} +} + +proc update_MODELPARAM_VALUE.wb_data_bits { MODELPARAM_VALUE.wb_data_bits PARAM_VALUE.wb_data_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb_data_bits}] ${MODELPARAM_VALUE.wb_data_bits} +} + +proc update_MODELPARAM_VALUE.wb_sel_bits { MODELPARAM_VALUE.wb_sel_bits PARAM_VALUE.wb_sel_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb_sel_bits}] ${MODELPARAM_VALUE.wb_sel_bits} +} + +proc update_MODELPARAM_VALUE.wb2_sel_bits { MODELPARAM_VALUE.wb2_sel_bits PARAM_VALUE.wb2_sel_bits } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.wb2_sel_bits}] ${MODELPARAM_VALUE.wb2_sel_bits} +} + +proc update_MODELPARAM_VALUE.cmd_len { MODELPARAM_VALUE.cmd_len PARAM_VALUE.cmd_len } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.cmd_len}] ${MODELPARAM_VALUE.cmd_len} +} + +proc update_MODELPARAM_VALUE.AXI_LSBS { MODELPARAM_VALUE.AXI_LSBS PARAM_VALUE.AXI_LSBS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_LSBS}] ${MODELPARAM_VALUE.AXI_LSBS} +} + +proc update_MODELPARAM_VALUE.AXI_ADDR_WIDTH { MODELPARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH} +} +