diff --git a/rtl/axi_addr.v b/rtl/axi/axi_addr.v similarity index 100% rename from rtl/axi_addr.v rename to rtl/axi/axi_addr.v diff --git a/rtl/axim2wbsp.v b/rtl/axi/axim2wbsp.v similarity index 100% rename from rtl/axim2wbsp.v rename to rtl/axi/axim2wbsp.v diff --git a/rtl/aximrd2wbsp.v b/rtl/axi/aximrd2wbsp.v similarity index 100% rename from rtl/aximrd2wbsp.v rename to rtl/axi/aximrd2wbsp.v diff --git a/rtl/aximwr2wbsp.v b/rtl/axi/aximwr2wbsp.v similarity index 100% rename from rtl/aximwr2wbsp.v rename to rtl/axi/aximwr2wbsp.v diff --git a/rtl/ddr3_top_axi.v b/rtl/axi/ddr3_top_axi.v similarity index 100% rename from rtl/ddr3_top_axi.v rename to rtl/axi/ddr3_top_axi.v diff --git a/rtl/sfifo.v b/rtl/axi/sfifo.v similarity index 100% rename from rtl/sfifo.v rename to rtl/axi/sfifo.v diff --git a/rtl/skidbuffer.v b/rtl/axi/skidbuffer.v similarity index 100% rename from rtl/skidbuffer.v rename to rtl/axi/skidbuffer.v diff --git a/rtl/wbarbiter.v b/rtl/axi/wbarbiter.v similarity index 100% rename from rtl/wbarbiter.v rename to rtl/axi/wbarbiter.v diff --git a/rtl/migsdram.v b/rtl/migsdram.v deleted file mode 100644 index c1671c8..0000000 --- a/rtl/migsdram.v +++ /dev/null @@ -1,313 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: migsdram.v -// {{{ -// Project: WB2AXIPSP: bus bridges and other odds and ends -// -// Purpose: This file isn't really a part of the synthesis implementation -// of the wb2axip project itself, but rather it is an example -// of how the wb2axip project can be used to connect a MIG generated -// IP component. -// -// This implementation depends upon the existence of a MIG generated -// core, named "mig_axis", and illustrates how such a core might be -// connected to the wbm2axip bridge. Specific options of the mig_axis -// setup include 6 identifier bits, and a full-sized bus width of 128 -// bits. These two settings are both appropriate for driving a DDR3 -// memory (whose minimum transfer size is 128 bits), but may need to be -// adjusted to support other memories. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2015-2024, Gisselquist Technology, LLC -// {{{ -// This file is part of the WB2AXIP project. -// -// The WB2AXIP project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset, - // Wishbone components - i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, - o_wb_ack, o_wb_stall, o_wb_data, o_wb_err, - // SDRAM connections - o_ddr_ck_p, o_ddr_ck_n, - o_ddr_reset_n, o_ddr_cke, - o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n, - o_ddr_ba, o_ddr_addr, - o_ddr_odt, o_ddr_dm, - io_ddr_dqs_p, io_ddr_dqs_n, - io_ddr_data - ); - parameter DDRWIDTH = 16, WBDATAWIDTH=32; - parameter AXIDWIDTH = 6; - // The SDRAM address bits (RAMABITS) are a touch more difficult to work - // out. Here we leave them as a fixed parameter, but there are - // consequences to this. Specifically, the wishbone data width, the - // wishbone address width, and this number have interactions not - // well captured here. - parameter RAMABITS = 28; - // All DDR3 memories have 8 timeslots. This, if the DDR3 memory - // has 16 bits to it (as above), the entire transaction must take - // AXIWIDTH bits ... - localparam AXIWIDTH= DDRWIDTH *8; - localparam DW=WBDATAWIDTH; - localparam AW=(WBDATAWIDTH==32)? RAMABITS-2 - :((WBDATAWIDTH==64) ? RAMABITS-3 - :((WBDATAWIDTH==128) ? RAMABITS-4 - : RAMABITS-5)); // (WBDATAWIDTH==256) - localparam SELW= (WBDATAWIDTH/8); - // - input wire i_clk, i_clk_200mhz, i_rst; - output wire o_sys_clk; - output reg o_sys_reset; - // - input wire i_wb_cyc, i_wb_stb, i_wb_we; - input wire [(AW-1):0] i_wb_addr; - input wire [(DW-1):0] i_wb_data; - input wire [(SELW-1):0] i_wb_sel; - output wire o_wb_ack, o_wb_stall; - output wire [(DW-1):0] o_wb_data; - output wire o_wb_err; - // - output wire [0:0] o_ddr_ck_p, o_ddr_ck_n; - output wire [0:0] o_ddr_cke; - output wire o_ddr_reset_n, - o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n; - output wire [0:0] o_ddr_cs_n; - output wire [2:0] o_ddr_ba; - output wire [13:0] o_ddr_addr; - output wire [0:0] o_ddr_odt; - output wire [(DDRWIDTH/8-1):0] o_ddr_dm; - inout wire [1:0] io_ddr_dqs_p, io_ddr_dqs_n; - inout wire [(DDRWIDTH-1):0] io_ddr_data; - - -`define SDRAM_ACCESS -`ifdef SDRAM_ACCESS - - wire aresetn; - assign aresetn = 1'b1; // Never reset - - // Write address channel - wire [(AXIDWIDTH-1):0] s_axi_awid; - wire [(RAMABITS-1):0] s_axi_awaddr; - wire [7:0] s_axi_awlen; - wire [2:0] s_axi_awsize; - wire [1:0] s_axi_awburst; - wire [0:0] s_axi_awlock; - wire [3:0] s_axi_awcache; - wire [2:0] s_axi_awprot; - wire [3:0] s_axi_awqos; - wire s_axi_awvalid; - wire s_axi_awready; - // Writei data channel - wire [(AXIWIDTH-1):0] s_axi_wdata; - wire [(AXIWIDTH/8-1):0] s_axi_wstrb; - wire s_axi_wlast, s_axi_wvalid, s_axi_wready; - // Write response channel - wire s_axi_bready; - wire [(AXIDWIDTH-1):0] s_axi_bid; - wire [1:0] s_axi_bresp; - wire s_axi_bvalid; - - // Read address channel - wire [(AXIDWIDTH-1):0] s_axi_arid; - wire [(RAMABITS-1):0] s_axi_araddr; - wire [7:0] s_axi_arlen; - wire [2:0] s_axi_arsize; - wire [1:0] s_axi_arburst; - wire [0:0] s_axi_arlock; - wire [3:0] s_axi_arcache; - wire [2:0] s_axi_arprot; - wire [3:0] s_axi_arqos; - wire s_axi_arvalid; - wire s_axi_arready; - // Read response/data channel - wire [(AXIDWIDTH-1):0] s_axi_rid; - wire [(AXIWIDTH-1):0] s_axi_rdata; - wire [1:0] s_axi_rresp; - wire s_axi_rlast; - wire s_axi_rvalid; - wire s_axi_rready; - - // Other wires ... - wire init_calib_complete, mmcm_locked; - wire app_sr_active, app_ref_ack, app_zq_ack; - wire app_sr_req, app_ref_req, app_zq_req; - wire w_sys_reset; - wire [11:0] w_device_temp; - - - mig_axis mig_sdram( - .ddr3_ck_p(o_ddr_ck_p), .ddr3_ck_n(o_ddr_ck_n), - .ddr3_reset_n(o_ddr_reset_n), .ddr3_cke(o_ddr_cke), - .ddr3_cs_n(o_ddr_cs_n), .ddr3_ras_n(o_ddr_ras_n), - .ddr3_we_n(o_ddr_we_n), .ddr3_cas_n(o_ddr_cas_n), - .ddr3_ba(o_ddr_ba), .ddr3_addr(o_ddr_addr), - .ddr3_odt(o_ddr_odt), - .ddr3_dqs_p(io_ddr_dqs_p), .ddr3_dqs_n(io_ddr_dqs_n), - .ddr3_dq(io_ddr_data), .ddr3_dm(o_ddr_dm), - // - .sys_clk_i(i_clk), - .clk_ref_i(i_clk_200mhz), - .ui_clk(o_sys_clk), - .ui_clk_sync_rst(w_sys_reset), - .mmcm_locked(mmcm_locked), - .aresetn(aresetn), - .app_sr_req(1'b0), - .app_ref_req(1'b0), - .app_zq_req(1'b0), - .app_sr_active(app_sr_active), - .app_ref_ack(app_ref_ack), - .app_zq_ack(app_zq_ack), - // - .s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr), - .s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize), - .s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock), - .s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot), - .s_axi_awqos(s_axi_awqos), .s_axi_awvalid(s_axi_awvalid), - .s_axi_awready(s_axi_awready), - // - .s_axi_wready( s_axi_wready), - .s_axi_wdata( s_axi_wdata), - .s_axi_wstrb( s_axi_wstrb), - .s_axi_wlast( s_axi_wlast), - .s_axi_wvalid( s_axi_wvalid), - // - .s_axi_bready(s_axi_bready), .s_axi_bid(s_axi_bid), - .s_axi_bresp(s_axi_bresp), .s_axi_bvalid(s_axi_bvalid), - // - .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), - .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), - .s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock), - .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), - .s_axi_arqos(s_axi_arqos), .s_axi_arvalid(s_axi_arvalid), - .s_axi_arready(s_axi_arready), - // - .s_axi_rready(s_axi_rready), .s_axi_rid(s_axi_rid), - .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), - .s_axi_rlast(s_axi_rlast), .s_axi_rvalid(s_axi_rvalid), - .init_calib_complete(init_calib_complete), - .sys_rst(i_rst), - .device_temp(w_device_temp) - ); - - wbm2axisp #( - .C_AXI_ID_WIDTH(AXIDWIDTH), - .C_AXI_DATA_WIDTH(AXIWIDTH), - .C_AXI_ADDR_WIDTH(RAMABITS), - .AW(AW), .DW(DW) - ) - bus_translator( - .i_clk(o_sys_clk), - // .i_reset(i_rst), // internally unused - // Write address channel signals - .o_axi_awvalid( s_axi_awvalid), - .i_axi_awready( s_axi_awready), - .o_axi_awid( s_axi_awid), - .o_axi_awaddr( s_axi_awaddr), - .o_axi_awlen( s_axi_awlen), - .o_axi_awsize( s_axi_awsize), - .o_axi_awburst( s_axi_awburst), - .o_axi_awlock( s_axi_awlock), - .o_axi_awcache( s_axi_awcache), - .o_axi_awprot( s_axi_awprot), // s_axi_awqos - .o_axi_awqos( s_axi_awqos), // s_axi_awqos - // - .o_axi_wvalid( s_axi_wvalid), - .i_axi_wready( s_axi_wready), - .o_axi_wdata( s_axi_wdata), - .o_axi_wstrb( s_axi_wstrb), - .o_axi_wlast( s_axi_wlast), - // - .i_axi_bvalid( s_axi_bvalid), - .o_axi_bready( s_axi_bready), - .i_axi_bid( s_axi_bid), - .i_axi_bresp( s_axi_bresp), - // - .o_axi_arvalid( s_axi_arvalid), - .i_axi_arready( s_axi_arready), - .o_axi_arid( s_axi_arid), - .o_axi_araddr( s_axi_araddr), - .o_axi_arlen( s_axi_arlen), - .o_axi_arsize( s_axi_arsize), - .o_axi_arburst( s_axi_arburst), - .o_axi_arlock( s_axi_arlock), - .o_axi_arcache( s_axi_arcache), - .o_axi_arprot( s_axi_arprot), - .o_axi_arqos( s_axi_arqos), - // - .i_axi_rvalid( s_axi_rvalid), - .o_axi_rready( s_axi_rready), - .i_axi_rid( s_axi_rid), - .i_axi_rdata( s_axi_rdata), - .i_axi_rresp( s_axi_rresp), - .i_axi_rlast( s_axi_rlast), - // - .i_wb_cyc( i_wb_cyc), - .i_wb_stb( i_wb_stb), - .i_wb_we( i_wb_we), - .i_wb_addr( i_wb_addr), - .i_wb_data( i_wb_data), - .i_wb_sel( i_wb_sel), - // - .o_wb_stall( o_wb_stall), - .o_wb_ack( o_wb_ack), - .o_wb_data( o_wb_data), - .o_wb_err( o_wb_err) - ); - - // Convert from active low to active high, *and* hold the system in - // reset until the memory comes up. - initial o_sys_reset = 1'b1; - always @(posedge o_sys_clk) - o_sys_reset <= (!w_sys_reset) - ||(!init_calib_complete) - ||(!mmcm_locked); -`else - BUFG sysclk(i_clk, o_sys_clk); - initial o_sys_reset <= 1'b1; - always @(posedge i_clk) - o_sys_reset <= 1'b1; - - OBUFDS ckobuf(.I(i_clk), .O(o_ddr_ck_p), .OB(o_ddr_ck_n)); - - assign o_ddr_reset_n = 1'b0; - assign o_ddr_cke[0] = 1'b0; - assign o_ddr_cs_n[0] = 1'b1; - assign o_ddr_cas_n = 1'b1; - assign o_ddr_ras_n = 1'b1; - assign o_ddr_we_n = 1'b1; - assign o_ddr_ba = 3'h0; - assign o_ddr_addr = 14'h00; - assign o_ddr_dm = 2'b00; - assign io_ddr_data = 16'h0; - - OBUFDS dqsbufa(.I(i_clk), .O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1])); - OBUFDS dqsbufb(.I(i_clk), .O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0])); - -`endif - -endmodule -`ifndef YOSYS -`default_nettype wire -`endif diff --git a/testbench/axi_tb/addr.coe b/testbench/axi_tb/addr.coe new file mode 100644 index 0000000..fc3263f --- /dev/null +++ b/testbench/axi_tb/addr.coe @@ -0,0 +1,258 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00000000 +00000000 +00000010 +00000010 +00000020 +00000020 +00000030 +00000030 +00000040 +00000040 +00000050 +00000050 +00000060 +00000060 +00000070 +00000070 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +; diff --git a/testbench/axi_tb/ctrl.coe b/testbench/axi_tb/ctrl.coe new file mode 100644 index 0000000..4da9bf0 --- /dev/null +++ b/testbench/axi_tb/ctrl.coe @@ -0,0 +1,258 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00030100 +00020201 +00030302 +00020403 +00030504 +00020605 +00030706 +00020807 +00030908 +00020a09 +00030b0a +00020c0b +00030d0c +00020e0d +00030f0e +0002100f +00031110 +00031211 +00031312 +00031413 +00031514 +00031615 +00031716 +00031817 +00031918 +00031a19 +00031b1a +00031c1b +00031d1c +00031e1d +00031f1e +0003201f +00032120 +00032221 +00032322 +00032423 +00032524 +00032625 +00032726 +00032827 +00032928 +00032a29 +00032b2a +00032c2b +00032d2c +00032e2d +00032f2e +0003302f +00033130 +00033231 +00033332 +00033433 +00033534 +00033635 +00033736 +00033837 +00033938 +00033a39 +00033b3a +00033c3b +00033d3c +00033e3d +00033f3e +0003403f +00034140 +00034241 +00034342 +00034443 +00034544 +00034645 +00034746 +00034847 +00034948 +00034a49 +00034b4a +00034c4b +00034d4c +00034e4d +00034f4e +0003504f +00035150 +00035251 +00035352 +00035453 +00035554 +00035655 +00035756 +00035857 +00035958 +00035a59 +00035b5a +00035c5b +00035d5c +00035e5d +00035f5e +0003605f +00036160 +00036261 +00036362 +00036463 +00036564 +00036665 +00036766 +00036867 +00036968 +00036a69 +00036b6a +00036c6b +00036d6c +00036e6d +00036f6e +0003706f +00037170 +00037271 +00037372 +00037473 +00037574 +00037675 +00037776 +00037877 +00037978 +00037a79 +00037b7a +00037c7b +00037d7c +00037e7d +00037f7e +0003807f +00038180 +00038281 +00038382 +00038483 +00038584 +00038685 +00038786 +00038887 +00038988 +00038a89 +00038b8a +00038c8b +00038d8c +00038e8d +00038f8e +0003908f +00039190 +00039291 +00039392 +00039493 +00039594 +00039695 +00039796 +00039897 +00039998 +00039a99 +00039b9a +00039c9b +00039d9c +00039e9d +00039f9e +0003a09f +0003a1a0 +0003a2a1 +0003a3a2 +0003a4a3 +0003a5a4 +0003a6a5 +0003a7a6 +0003a8a7 +0003a9a8 +0003aaa9 +0003abaa +0003acab +0003adac +0003aead +0003afae +0003b0af +0003b1b0 +0003b2b1 +0003b3b2 +0003b4b3 +0003b5b4 +0003b6b5 +0003b7b6 +0003b8b7 +0003b9b8 +0003bab9 +0003bbba +0003bcbb +0003bdbc +0003bebd +0003bfbe +0003c0bf +0003c1c0 +0003c2c1 +0003c3c2 +0003c4c3 +0003c5c4 +0003c6c5 +0003c7c6 +0003c8c7 +0003c9c8 +0003cac9 +0003cbca +0003cccb +0003cdcc +0003cecd +0003cfce +0003d0cf +0003d1d0 +0003d2d1 +0003d3d2 +0003d4d3 +0003d5d4 +0003d6d5 +0003d7d6 +0003d8d7 +0003d9d8 +0003dad9 +0003dbda +0003dcdb +0003dddc +0003dedd +0003dfde +0003e0df +0003e1e0 +0003e2e1 +0003e3e2 +0003e4e3 +0003e5e4 +0003e6e5 +0003e7e6 +0003e8e7 +0003e9e8 +0003eae9 +0003ebea +0003eceb +0003edec +0003eeed +0003efee +0003f0ef +0003f1f0 +0003f2f1 +0003f3f2 +0003f4f3 +0003f5f4 +0003f6f5 +0003f7f6 +0003f8f7 +0003f9f8 +0003faf9 +0003fbfa +0003fcfb +0003fdfc +0003fefd +0003fffe +; diff --git a/testbench/axi_tb/data.atg b/testbench/axi_tb/data.atg new file mode 100644 index 0000000..8448bd0 Binary files /dev/null and b/testbench/axi_tb/data.atg differ diff --git a/testbench/axi_tb/data.coe b/testbench/axi_tb/data.coe new file mode 100644 index 0000000..df830cb --- /dev/null +++ b/testbench/axi_tb/data.coe @@ -0,0 +1,258 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +01234567 +00000000 +89abcdef +00000000 +19283746 +00000000 +afdec70a +00000000 +12121212 +00000000 +34343434 +00000000 +00000000 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +; diff --git a/testbench/axi_tb/ddr3_axi_traffic_gen_behav.wcfg b/testbench/axi_tb/ddr3_axi_traffic_gen_behav.wcfg new file mode 100644 index 0000000..ecee334 --- /dev/null +++ b/testbench/axi_tb/ddr3_axi_traffic_gen_behav.wcfg @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + i_controller_clk + i_controller_clk + + + i_ddr3_clk + i_ddr3_clk + + + i_ref_clk + i_ref_clk + + + i_ddr3_clk_90 + i_ddr3_clk_90 + + + i_rst_n + i_rst_n + + + AXI Lite (Traffic Generator) + label + + + s_axi_aclk + s_axi_aclk + + + s_axi_aresetn + s_axi_aresetn + + + m_axi_lite_ch1_awaddr[31:0] + m_axi_lite_ch1_awaddr[31:0] + + + m_axi_lite_ch1_awprot[2:0] + m_axi_lite_ch1_awprot[2:0] + + + m_axi_lite_ch1_awvalid + m_axi_lite_ch1_awvalid + + + m_axi_lite_ch1_awready + m_axi_lite_ch1_awready + + + m_axi_lite_ch1_wdata[31:0] + m_axi_lite_ch1_wdata[31:0] + + + m_axi_lite_ch1_wstrb[3:0] + m_axi_lite_ch1_wstrb[3:0] + + + m_axi_lite_ch1_wvalid + m_axi_lite_ch1_wvalid + + + m_axi_lite_ch1_wready + m_axi_lite_ch1_wready + + + m_axi_lite_ch1_bresp[1:0] + m_axi_lite_ch1_bresp[1:0] + + + m_axi_lite_ch1_bvalid + m_axi_lite_ch1_bvalid + + + m_axi_lite_ch1_bready + m_axi_lite_ch1_bready + + + m_axi_lite_ch1_araddr[31:0] + m_axi_lite_ch1_araddr[31:0] + + + m_axi_lite_ch1_arvalid + m_axi_lite_ch1_arvalid + + + m_axi_lite_ch1_arready + m_axi_lite_ch1_arready + + + m_axi_lite_ch1_rdata[31:0] + m_axi_lite_ch1_rdata[31:0] + + + m_axi_lite_ch1_rvalid + m_axi_lite_ch1_rvalid + + + m_axi_lite_ch1_rresp[1:0] + m_axi_lite_ch1_rresp[1:0] + + + m_axi_lite_ch1_rready + m_axi_lite_ch1_rready + + + done + done + + + status[31:0] + status[31:0] + UNSIGNEDDECRADIX + + + s_axi_wdata[127:0] + s_axi_wdata[127:0] + + + s_axi_wstrb[15:0] + s_axi_wstrb[15:0] + + + Controller + label + + + instruction_address[4:0] + instruction_address[4:0] + + + state_calibrate[5:0] + state_calibrate[5:0] + UNSIGNEDDECRADIX + + + lane[0:0] + lane[0:0] + + + correct_read_data[31:0] + correct_read_data[31:0] + + + wrong_read_data[31:0] + wrong_read_data[31:0] + + + i_wb_cyc + i_wb_cyc + + + i_wb_stb + i_wb_stb + + + i_wb_we + i_wb_we + + + i_wb_addr[23:0] + i_wb_addr[23:0] + + + i_wb_data[127:0] + i_wb_data[127:0] + + + i_wb_sel[15:0] + i_wb_sel[15:0] + + + o_wb_stall + o_wb_stall + + + o_wb_ack + o_wb_ack + + + o_wb_data[127:0] + o_wb_data[127:0] + + diff --git a/testbench/ddr3_axi_traffic_gen.sv b/testbench/axi_tb/ddr3_axi_traffic_gen_tb.sv similarity index 98% rename from testbench/ddr3_axi_traffic_gen.sv rename to testbench/axi_tb/ddr3_axi_traffic_gen_tb.sv index ac568db..cb7aa68 100644 --- a/testbench/ddr3_axi_traffic_gen.sv +++ b/testbench/axi_tb/ddr3_axi_traffic_gen_tb.sv @@ -1,4 +1,4 @@ -module ddr3_axi_traffic_gen; +module ddr3_axi_traffic_gen_tb; reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90; reg i_rst_n; @@ -68,7 +68,7 @@ wire m_axi_lite_ch1_rready; wire done; wire [31 : 0] status; -axi_traffic_gen_1 axi_traffic_gen_inst( +axi_traffic_gen_0 axi_traffic_gen_inst( .s_axi_aclk(i_controller_clk), .s_axi_aresetn(i_rst_n && (dut.ddr3_top_inst.ddr3_controller_inst.state_calibrate == 23)), //stay reset until calibration is done .m_axi_lite_ch1_awaddr(m_axi_lite_ch1_awaddr), diff --git a/testbench/axi_tb/mask.coe b/testbench/axi_tb/mask.coe new file mode 100644 index 0000000..5db962a --- /dev/null +++ b/testbench/axi_tb/mask.coe @@ -0,0 +1,258 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +; diff --git a/testbench/ddr3_axi.sv b/testbench/ddr3_axi.sv deleted file mode 100644 index 7129c00..0000000 --- a/testbench/ddr3_axi.sv +++ /dev/null @@ -1,282 +0,0 @@ -module ddr3_axi_tb; - -reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90; -reg i_rst_n; - -// AXI Interface -// AXI write address channel signals -reg s_axi_awvalid; -wire s_axi_awready; -reg [dut.AXI_ID_WIDTH-1:0] s_axi_awid; -reg [dut.AXI_ADDR_WIDTH-1:0] s_axi_awaddr; -// AXI write data channel signals -reg s_axi_wvalid; -wire s_axi_wready; -reg [dut.AXI_DATA_WIDTH-1:0] s_axi_wdata; -reg [dut.AXI_DATA_WIDTH/8-1:0] s_axi_wstrb; -reg s_axi_wlast; -// AXI write response channel signals -wire s_axi_bvalid; -reg s_axi_bready; -wire [dut.AXI_ID_WIDTH-1:0] s_axi_bid; -wire [1:0] s_axi_bresp; -// AXI read address channel signals -reg s_axi_arvalid; -wire s_axi_arready; -reg [dut.AXI_ID_WIDTH-1:0] s_axi_arid; -reg [dut.AXI_ADDR_WIDTH-1:0] s_axi_araddr; -// AXI read data channel signals -wire s_axi_rvalid; // rd rslt valid -reg s_axi_rready; // rd rslt ready -wire [dut.AXI_ID_WIDTH-1:0] s_axi_rid; // response id -wire [dut.AXI_DATA_WIDTH-1:0] s_axi_rdata;// read data -wire s_axi_rlast; // read last -wire [1:0] s_axi_rresp; // read response - -// DDR3 Pins -wire o_ddr3_clk_p; -wire o_ddr3_clk_n; -wire o_ddr3_reset_n; -wire o_ddr3_cke; -wire o_ddr3_cs_n; -wire o_ddr3_ras_n; -wire o_ddr3_cas_n; -wire o_ddr3_we_n; -wire[dut.ROW_BITS-1:0] o_ddr3_addr; -wire[dut.BA_BITS-1:0] o_ddr3_ba_addr; -wire[(dut.DQ_BITS*dut.BYTE_LANES)-1:0] io_ddr3_dq; -wire[dut.BYTE_LANES-1:0] io_ddr3_dqs, io_ddr3_dqs_n; -wire[dut.BYTE_LANES-1:0] o_ddr3_dm; -wire o_ddr3_odt; - - localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module - DDR3_CLK_PERIOD = 2500; //ps, period of clock input to DDR3 RAM device - - -// Clocks and reset - always #(CONTROLLER_CLK_PERIOD/2) i_controller_clk = !i_controller_clk; - always #(DDR3_CLK_PERIOD/2) i_ddr3_clk = !i_ddr3_clk; - always #2500 i_ref_clk = !i_ref_clk; - initial begin //90 degree phase shifted ddr3_clk - #(DDR3_CLK_PERIOD/4); - while(1) begin - #(DDR3_CLK_PERIOD/2) i_ddr3_clk_90 = !i_ddr3_clk_90; - end - end - initial begin - i_controller_clk = 1; - i_ddr3_clk = 1; - i_ref_clk = 1; - i_ddr3_clk_90 = 1; - i_rst_n = 0; - #1_000_000; - i_rst_n = 1; - end - -initial begin - // initialize AXI - s_axi_awvalid = 0; - s_axi_awid = 0; - s_axi_awaddr = 0; - - s_axi_wvalid = 0; - s_axi_wdata = 0; - s_axi_wstrb = 0; - s_axi_wlast = 0; - - s_axi_bready = 0; - - s_axi_arvalid = 0; - s_axi_arid = 0; - s_axi_araddr = 0; - - s_axi_rready = 0; - - //wait until done calibrate - wait(dut.ddr3_top_inst.ddr3_controller_inst.state_calibrate == 23); - - // write data to address 3 (0-15 = address 0, 16-31 = address 1, 32-47 = address 2) - @(negedge i_controller_clk); - s_axi_awvalid = 1; - s_axi_awid = 0; - s_axi_awaddr = 33; - @(negedge i_controller_clk); - // while(!s_axi_awready) begin - // @(negedge i_controller_clk); - // end - s_axi_awvalid = 0; - s_axi_awid = 0; - s_axi_awaddr = 0; - - s_axi_wvalid = 1; - s_axi_wdata = 128'hAAAA_BBBB_CCCC_DDDD_EEEE_FFFF_0000_1111; // data 1 - s_axi_wstrb = -1; - - @(negedge i_controller_clk); - while(!s_axi_wready) begin - @(negedge i_controller_clk); - end - s_axi_wdata = 128'h2222_3333_4444_5555_6666_7777_8888_9999; // data 2 - - @(negedge i_controller_clk); - while(!s_axi_wready) begin - @(negedge i_controller_clk); - end - s_axi_wdata = 100; // data 3 - - @(negedge i_controller_clk); - while(!s_axi_wready) begin - @(negedge i_controller_clk); - end - s_axi_wdata = 2000; // data 4 - s_axi_wlast = 1; - - @(negedge i_controller_clk); - while(!s_axi_wready) begin - @(negedge i_controller_clk); - end - s_axi_wvalid = 0; - s_axi_wdata = 0; - s_axi_wstrb = 0; - s_axi_wlast = 0; - // DONE write data to address 3 - - // wait for write response - wait(s_axi_bvalid); - @(negedge i_controller_clk); - s_axi_bready = 1; - @(negedge i_controller_clk); - s_axi_bready = 0; - // done waiting for write response - - #1000_000; - // read data request from address 2 (0-15 = address 0, 16-31 = address 1, 32-47 = address 2) - @(negedge i_controller_clk); - s_axi_arvalid = 1; - s_axi_arid = 2; - s_axi_araddr = 46; - @(negedge i_controller_clk); - s_axi_arvalid = 0; - s_axi_arid = 0; - s_axi_araddr = 0; - // done read data request from address 3 - - // wait for read data - wait(s_axi_rvalid); - @(negedge i_controller_clk); - @(negedge i_controller_clk); - @(negedge i_controller_clk); - @(negedge i_controller_clk); - s_axi_rready = 1; - @(negedge i_controller_clk); - @(negedge i_controller_clk); - @(negedge i_controller_clk); - @(negedge i_controller_clk); - s_axi_rready = 0; - #1000_000; - $finish; - -end -ddr3_top_axi #( - .CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface - .DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) - .ROW_BITS(14), //width of row address - .COL_BITS(10), //width of column address - .BA_BITS(3), //width of bank address - .BYTE_LANES(2), //number of byte lanes of DDR3 RAM - .AXI_ID_WIDTH(4), // The AXI id width used for R&W, an int between 1-16 - .MICRON_SIM(1), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW) - .ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported - .SECOND_WISHBONE(0) //set to 1 if 2nd wishbone for debugging is needed -) dut - ( - .i_controller_clk(i_controller_clk), - .i_ddr3_clk(i_ddr3_clk), - .i_ref_clk(i_ref_clk), //i_controller_clk = CONTROLLER_CLK_PERIOD, i_ddr3_clk = DDR3_CLK_PERIOD, i_ref_clk = 200MHz - .i_ddr3_clk_90(i_ddr3_clk_90), //required only when ODELAY_SUPPORTED is zero - .i_rst_n(i_rst_n), - // - // AXI Interface - // AXI write address channel signals - .s_axi_awvalid(s_axi_awvalid), - .s_axi_awready(s_axi_awready), - .s_axi_awid(s_axi_awid), - .s_axi_awaddr(s_axi_awaddr), - .s_axi_awlen(3), // 4 transfers in a transaction - .s_axi_awsize($clog2(128)), - .s_axi_awburst(1), //incrementing burst address - .s_axi_awlock(0), - .s_axi_awcache(0), - .s_axi_awprot(0), - .s_axi_awqos(0), - // AXI write data channel signals - .s_axi_wvalid(s_axi_wvalid), - .s_axi_wready(s_axi_wready), - .s_axi_wdata(s_axi_wdata), - .s_axi_wstrb(s_axi_wstrb), - .s_axi_wlast(s_axi_wlast), - // AXI write response channel signals - .s_axi_bvalid(s_axi_bvalid), - .s_axi_bready(s_axi_bready), - .s_axi_bid(s_axi_bid), - .s_axi_bresp(s_axi_bresp), - // AXI read address channel signals - .s_axi_arvalid(s_axi_arvalid), - .s_axi_arready(s_axi_arready), - .s_axi_arid(s_axi_arid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arlen(3), // only 1 transfer in a transaction - .s_axi_arsize($clog2(128)), - .s_axi_arburst(1), //incrementing burst address - .s_axi_arlock(0), - .s_axi_arcache(0), - .s_axi_arprot(0), - .s_axi_arqos(0), - // AXI read data channel signals - .s_axi_rvalid(s_axi_rvalid), // rd rslt valid - .s_axi_rready(s_axi_rready), // rd rslt ready - .s_axi_rid(s_axi_rid), // response id - .s_axi_rdata(s_axi_rdata),// read data - .s_axi_rlast(s_axi_rlast), // read last - .s_axi_rresp(s_axi_rresp), // read response - // - // DDR3 I/O Interface - .o_ddr3_clk_p(o_ddr3_clk_p), - .o_ddr3_clk_n(o_ddr3_clk_n), - .o_ddr3_reset_n(o_ddr3_reset_n), - .o_ddr3_cke(o_ddr3_cke), - .o_ddr3_cs_n(o_ddr3_cs_n), - .o_ddr3_ras_n(o_ddr3_ras_n), - .o_ddr3_cas_n(o_ddr3_cas_n), - .o_ddr3_we_n(o_ddr3_we_n), - .o_ddr3_addr(o_ddr3_addr), - .o_ddr3_ba_addr(o_ddr3_ba_addr), - .io_ddr3_dq(io_ddr3_dq), - .io_ddr3_dqs(io_ddr3_dqs), - .io_ddr3_dqs_n(io_ddr3_dqs_n), - .o_ddr3_dm(o_ddr3_dm), - .o_ddr3_odt(o_ddr3_odt) - // - ); - -ddr3 ddr3_0( - .rst_n(o_ddr3_reset_n), - .ck(o_ddr3_clk_p), - .ck_n(o_ddr3_clk_n), - .cke(o_ddr3_cke), - .cs_n(o_ddr3_cs_n), - .ras_n(o_ddr3_ras_n), - .cas_n(o_ddr3_cas_n), - .we_n(o_ddr3_we_n), - .dm_tdqs(o_ddr3_dm), - .ba(o_ddr3_ba_addr), - .addr({0,o_ddr3_addr}), - .dq(io_ddr3_dq), - .dqs(io_ddr3_dqs), - .dqs_n(io_ddr3_dqs_n), - .tdqs_n(), - .odt(o_ddr3_odt) - ); - - -endmodule \ No newline at end of file