add example demo for enclustra_kx2_st1
This commit is contained in:
AngeloJacobo
parent
8fb24dd180
commit
79a2c63bb8
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@ -139,7 +139,6 @@
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.ROW_BITS(14), //width of row address
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.COL_BITS(10), //width of column address
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.BA_BITS(3), //width of bank address
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.DQ_BITS(8), //width of DQ
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.BYTE_LANES(2), //number of DDR3 modules to be controlled
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.AUX_WIDTH(4), //width of aux line (must be >= 4)
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.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
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@ -0,0 +1,210 @@
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################################################################################
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################################################################################
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
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# set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18 } [get_ports {CLK_100_CAL}]
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set_property DCI_CASCADE {32 33} [get_iobanks 34]
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## For a 1.5V memory, the appropriate VREF voltage is half of 1.5, or 0.75 Volts
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## Of the DDR3 bank(s), only bank 33 needs the INTERNAL_VREF. The other DDR3
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## banks are explicitly connected to an external VREF signal. However, bank
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## 33s IOs are overloaded--there was no room for the VREF. Hence, to spare
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## two pins, bank 33 uses an internal voltage reference. Sadly, the same
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## problem plays out in banks 12-16 as well.
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set_property INTERNAL_VREF 0.750 [get_iobanks 33]
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## Other IO banks have internal VREFs as well, those these aren't as critical
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set_property INTERNAL_VREF 0.90 [get_iobanks 12]
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set_property INTERNAL_VREF 0.60 [get_iobanks 13]
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set_property INTERNAL_VREF 0.90 [get_iobanks 14]
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set_property INTERNAL_VREF 0.90 [get_iobanks 15]
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set_property INTERNAL_VREF 0.90 [get_iobanks 16]
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## Clocks
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# 100MHz single ended input clock
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set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15 } [get_ports {i_clk}];
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create_clock -name i_clk -period 10.000 [get_ports i_clk];
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# Baseboard LEDs
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# set_property -dict {SLEW SLOW PACKAGE_PIN F22 IOSTANDARD LVCMOS18 } [get_ports { o_led_status[4] }]; # GPIO0_LED0_N
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set_property -dict {SLEW SLOW PACKAGE_PIN E23 IOSTANDARD LVCMOS18 } [get_ports { led[0] }]; # GPIO1_LED1_N
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set_property -dict {SLEW SLOW PACKAGE_PIN K25 IOSTANDARD LVCMOS12 } [get_ports { led[1] }]; # LED2
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set_property -dict {SLEW SLOW PACKAGE_PIN K26 IOSTANDARD LVCMOS12 } [get_ports { led[2] }]; # LED3
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## UART
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## {{{
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18 } [get_ports {rx}]; # UART_RX
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set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 } [get_ports {tx}]; # UART_TX
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## }}}
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## Buttons
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## {{{
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set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18 } [get_ports {i_rst_n}]; # (Not in TCL)
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## DDR3 MEMORY
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set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_reset_n}];
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set_property -dict {PACKAGE_PIN AB12 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_clk_p}];
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_clk_n}];
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set_property -dict {PACKAGE_PIN AA13 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_cke}]; ## CKE
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## set_property -dict {SLEW SLOW PACKAGE_PIN AA3 IOSTANDARD LVCMOS15 } [get_ports {o_ddr3_vsel}];
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set_property -dict {PACKAGE_PIN Y12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_cs_n}];
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ras_n}]
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_cas_n}];
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_we_n}];
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_odt}];
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## Address lines
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set_property -dict {PACKAGE_PIN AE11 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[0]}];
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set_property -dict {PACKAGE_PIN AF9 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[1]}];
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set_property -dict {PACKAGE_PIN AD10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[2]}];
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set_property -dict {PACKAGE_PIN AB10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[3]}];
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set_property -dict {PACKAGE_PIN AA9 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[4]}];
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set_property -dict {PACKAGE_PIN AB9 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[5]}];
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set_property -dict {PACKAGE_PIN AA8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[6]}];
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set_property -dict {PACKAGE_PIN AC8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[7]}];
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set_property -dict {PACKAGE_PIN AA7 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[8]}];
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set_property -dict {PACKAGE_PIN AE8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[9]}];
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set_property -dict {PACKAGE_PIN AF10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[10]}];
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set_property -dict {PACKAGE_PIN AD8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[11]}];
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set_property -dict {PACKAGE_PIN AE10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[12]}];
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set_property -dict {PACKAGE_PIN AF8 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[13]}];
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set_property -dict {PACKAGE_PIN AC7 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_addr[14]}];
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set_property -dict {PACKAGE_PIN AD11 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ba[0]}];
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set_property -dict {PACKAGE_PIN AA10 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ba[1]}];
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_ba[2]}];
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## Byte lane #0
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set_property -dict {PACKAGE_PIN AA2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[0]}];
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set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[1]}];
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set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[2]}];
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set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[3]}];
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set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[4]}];
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set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[5]}];
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set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[6]}];
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set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[7]}];
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set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[0]}];
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set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[0]}];
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set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[0]}];
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## Byte lane #1
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set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[8]}];
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set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[9]}];
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set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[10]}];
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set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[11]}];
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set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[12]}];
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set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[13]}];
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set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[14]}];
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set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[15]}];
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set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[1]}];
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set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[1]}];
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set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[1]}];
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## Byte lane #2
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set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[16]}];
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set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[17]}];
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set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[18]}];
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set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[19]}];
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set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[20]}];
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set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[21]}];
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set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[22]}];
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set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[23]}];
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set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[2]}];
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set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[2]}];
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set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[2]}];
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## Byte lane #3
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set_property -dict {PACKAGE_PIN AD5 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[24]}];
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set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[25]}];
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set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[26]}];
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set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[27]}];
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set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[28]}];
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set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[29]}];
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set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[30]}];
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set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[31]}];
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set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[3]}];
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set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[3]}];
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[3]}];
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## Byte lane #4
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set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[32]}];
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[33]}];
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[34]}];
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[35]}];
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set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[36]}];
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set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[37]}];
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[38]}];
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set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[39]}];
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set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[4]}];
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set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[4]}];
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set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[4]}];
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## Byte lane #5
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[40]}];
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set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[41]}];
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[42]}];
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[43]}];
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set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[44]}];
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set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[45]}];
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set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[46]}];
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set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[47]}];
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set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[5]}];
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set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[5]}];
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[5]}];
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## Byte lane #6
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[48]}];
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set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[49]}];
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[50]}];
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set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[51]}];
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[52]}];
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set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[53]}];
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set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[54]}];
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set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[55]}];
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[6]}];
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set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[6]}];
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set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[6]}];
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## Byte lane #7
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set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[56]}];
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set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[57]}];
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||||
set_property -dict {PACKAGE_PIN W14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[58]}];
|
||||
set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[59]}];
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[60]}];
|
||||
set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[61]}];
|
||||
set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[62]}];
|
||||
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dq[63]}];
|
||||
|
||||
set_property -dict {PACKAGE_PIN V14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH } [get_ports {ddr3_dm[7]}];
|
||||
|
||||
set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_p[7]}];
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports {ddr3_dqs_n[7]}];
|
||||
|
||||
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Filename: enclustra_ddr3.v
|
||||
// Project: UberDDR3 - An Open Source DDR3 Controller
|
||||
//
|
||||
// Purpose: Example demo of UberDDR3 for Enclustra KX2-ST1 (xc7k160tffg676-2). Mechanism:
|
||||
// - three LEDs will light up once UberDDR3 is done calibrating
|
||||
// - if UART (9600 Baud Rate)receives small letter ASCII (a-z), this value will be written to DDR3
|
||||
// - if UART receives capital letter ASCII (A-Z), the small letter equivalent will be retrieved from DDR3 by doing
|
||||
// - a read request, once read data is available this will be sent to UART to be streamed out.
|
||||
// THUS:
|
||||
// - Sendng "abcdefg" to the UART terminal will store that small latter to DDR3
|
||||
// - Then sending "ABCDEFG" to the UART terminal will return the small letter equivalent: "abcdefg"
|
||||
//
|
||||
// Engineer: Angelo C. Jacobo
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2023-2024 Angelo Jacobo
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module enclustra_ddr3
|
||||
(
|
||||
input wire i_clk,
|
||||
input wire i_rst_n,
|
||||
// DDR3 I/O Interface
|
||||
output wire ddr3_clk_p, ddr3_clk_n,
|
||||
output wire ddr3_reset_n,
|
||||
output wire ddr3_cke,
|
||||
output wire ddr3_cs_n,
|
||||
output wire ddr3_ras_n,
|
||||
output wire ddr3_cas_n,
|
||||
output wire ddr3_we_n,
|
||||
output wire[15-1:0] ddr3_addr,
|
||||
output wire[3-1:0] ddr3_ba,
|
||||
inout wire[64-1:0] ddr3_dq,
|
||||
inout wire[8-1:0] ddr3_dqs_p, ddr3_dqs_n,
|
||||
output wire[8-1:0] ddr3_dm,
|
||||
output wire ddr3_odt,
|
||||
// UART line
|
||||
input wire rx,
|
||||
output wire tx,
|
||||
//Debug LEDs
|
||||
output wire[2:0] led
|
||||
);
|
||||
|
||||
wire i_controller_clk, i_ddr3_clk, i_ref_clk;
|
||||
wire m_axis_tvalid;
|
||||
wire rx_empty;
|
||||
wire tx_full;
|
||||
wire o_wb_ack;
|
||||
wire[7:0] o_wb_data;
|
||||
wire o_aux;
|
||||
wire[7:0] rd_data;
|
||||
wire o_wb_stall;
|
||||
reg i_wb_stb = 0, i_wb_we;
|
||||
wire[63:0] o_debug1;
|
||||
reg[7:0] i_wb_data;
|
||||
reg[7:0] i_wb_addr;
|
||||
// o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
|
||||
assign led[0] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
|
||||
assign led[1] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
|
||||
assign led[2] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
|
||||
|
||||
always @(posedge i_controller_clk) begin
|
||||
begin
|
||||
i_wb_stb <= 0;
|
||||
i_wb_we <= 0;
|
||||
i_wb_addr <= 0;
|
||||
i_wb_data <= 0;
|
||||
if(!o_wb_stall && m_axis_tvalid) begin
|
||||
if(rd_data >= 97 && rd_data <= 122) begin //write to DDR3 if ASCII is small letter
|
||||
i_wb_stb <= 1;
|
||||
i_wb_we <= 1;
|
||||
i_wb_addr <= ~rd_data ;
|
||||
i_wb_data <= rd_data;
|
||||
end
|
||||
else if(rd_data >= 65 && rd_data <= 90) begin //read from DDR3 if ASCII is capital letter
|
||||
i_wb_stb <= 1; //make request
|
||||
i_wb_we <= 0; //read
|
||||
i_wb_addr <= ~(rd_data + 8'd32);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire clk_locked;
|
||||
clk_wiz_0 clk_wiz_inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(i_controller_clk), //100 Mhz
|
||||
.clk_out2(i_ddr3_clk), // 400 MHz
|
||||
.clk_out3(i_ref_clk), // 200 MHz
|
||||
// Status and control signals
|
||||
.reset(!i_rst_n),
|
||||
.locked(clk_locked),
|
||||
// Clock in ports
|
||||
.clk_in1(i_clk)
|
||||
);
|
||||
|
||||
// UART module from https://github.com/alexforencich/verilog-uart
|
||||
uart #(.DATA_WIDTH(8)) uart_m
|
||||
(
|
||||
.clk(i_controller_clk),
|
||||
.rst(!i_rst_n),
|
||||
.s_axis_tdata(o_wb_data),
|
||||
.s_axis_tvalid(o_wb_ack),
|
||||
.s_axis_tready(),
|
||||
.m_axis_tdata(rd_data),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(1),
|
||||
.rxd(rx),
|
||||
.txd(tx),
|
||||
.prescale(1302) //9600 Baud Rate: 100MHz/(8*9600)
|
||||
);
|
||||
|
||||
// DDR3 Controller
|
||||
ddr3_top #(
|
||||
.CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
|
||||
.DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
|
||||
.ROW_BITS(15), //width of row address
|
||||
.COL_BITS(10), //width of column address
|
||||
.BA_BITS(3), //width of bank address
|
||||
.BYTE_LANES(8), //number of DDR3 modules to be controlled
|
||||
.AUX_WIDTH(4), //width of aux line (must be >= 4)
|
||||
.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
|
||||
.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
|
||||
.MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
|
||||
.ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
|
||||
.SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed
|
||||
) ddr3_top
|
||||
(
|
||||
//clock and reset
|
||||
.i_controller_clk(i_controller_clk),
|
||||
.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
|
||||
.i_ref_clk(i_ref_clk),
|
||||
.i_ddr3_clk_90(0),
|
||||
.i_rst_n(i_rst_n && clk_locked),
|
||||
// Wishbone inputs
|
||||
.i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
|
||||
.i_wb_stb(i_wb_stb), //request a transfer
|
||||
.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
|
||||
.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
|
||||
.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
|
||||
.i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
|
||||
.i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
|
||||
// Wishbone outputs
|
||||
.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
|
||||
.o_wb_ack(o_wb_ack), //1 = read/write request has completed
|
||||
.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
|
||||
.o_aux(o_aux),
|
||||
// Wishbone 2 (PHY) inputs
|
||||
.i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
|
||||
.i_wb2_stb(), //request a transfer
|
||||
.i_wb2_we(), //write-enable (1 = write, 0 = read)
|
||||
.i_wb2_addr(), //burst-addressable {row,bank,col}
|
||||
.i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
|
||||
.i_wb2_sel(), //byte strobe for write (1 = write the byte)
|
||||
// Wishbone 2 (Controller) outputs
|
||||
.o_wb2_stall(), //1 = busy, cannot accept requests
|
||||
.o_wb2_ack(), //1 = read/write request has completed
|
||||
.o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
|
||||
// PHY Interface (to be added later)
|
||||
// DDR3 I/O Interface
|
||||
.o_ddr3_clk_p(ddr3_clk_p),
|
||||
.o_ddr3_clk_n(ddr3_clk_n),
|
||||
.o_ddr3_reset_n(ddr3_reset_n),
|
||||
.o_ddr3_cke(ddr3_cke), // CKE
|
||||
.o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
|
||||
.o_ddr3_ras_n(ddr3_ras_n), // RAS#
|
||||
.o_ddr3_cas_n(ddr3_cas_n), // CAS#
|
||||
.o_ddr3_we_n(ddr3_we_n), // WE#
|
||||
.o_ddr3_addr(ddr3_addr),
|
||||
.o_ddr3_ba_addr(ddr3_ba),
|
||||
.io_ddr3_dq(ddr3_dq),
|
||||
.io_ddr3_dqs(ddr3_dqs_p),
|
||||
.io_ddr3_dqs_n(ddr3_dqs_n),
|
||||
.o_ddr3_dm(ddr3_dm),
|
||||
.o_ddr3_odt(ddr3_odt), // on-die termination
|
||||
.o_debug1(o_debug1),
|
||||
.o_debug2(),
|
||||
.o_debug3()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream UART
|
||||
*/
|
||||
module uart #
|
||||
(
|
||||
parameter DATA_WIDTH = 8
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI input
|
||||
*/
|
||||
input wire [DATA_WIDTH-1:0] s_axis_tdata,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
|
||||
/*
|
||||
* AXI output
|
||||
*/
|
||||
output wire [DATA_WIDTH-1:0] m_axis_tdata,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
input wire rxd,
|
||||
output wire txd,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire tx_busy,
|
||||
output wire rx_busy,
|
||||
output wire rx_overrun_error,
|
||||
output wire rx_frame_error,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [15:0] prescale
|
||||
|
||||
);
|
||||
|
||||
uart_tx #(
|
||||
.DATA_WIDTH(DATA_WIDTH)
|
||||
)
|
||||
uart_tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// axi input
|
||||
.s_axis_tdata(s_axis_tdata),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
// output
|
||||
.txd(txd),
|
||||
// status
|
||||
.busy(tx_busy),
|
||||
// configuration
|
||||
.prescale(prescale)
|
||||
);
|
||||
|
||||
uart_rx #(
|
||||
.DATA_WIDTH(DATA_WIDTH)
|
||||
)
|
||||
uart_rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// axi output
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
// input
|
||||
.rxd(rxd),
|
||||
// status
|
||||
.busy(rx_busy),
|
||||
.overrun_error(rx_overrun_error),
|
||||
.frame_error(rx_frame_error),
|
||||
// configuration
|
||||
.prescale(prescale)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream UART
|
||||
*/
|
||||
module uart_rx #
|
||||
(
|
||||
parameter DATA_WIDTH = 8
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI output
|
||||
*/
|
||||
output wire [DATA_WIDTH-1:0] m_axis_tdata,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
input wire rxd,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
output wire overrun_error,
|
||||
output wire frame_error,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [15:0] prescale
|
||||
|
||||
);
|
||||
|
||||
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = 0;
|
||||
reg m_axis_tvalid_reg = 0;
|
||||
|
||||
reg rxd_reg = 1;
|
||||
|
||||
reg busy_reg = 0;
|
||||
reg overrun_error_reg = 0;
|
||||
reg frame_error_reg = 0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_reg = 0;
|
||||
reg [18:0] prescale_reg = 0;
|
||||
reg [3:0] bit_cnt = 0;
|
||||
|
||||
assign m_axis_tdata = m_axis_tdata_reg;
|
||||
assign m_axis_tvalid = m_axis_tvalid_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
assign overrun_error = overrun_error_reg;
|
||||
assign frame_error = frame_error_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
m_axis_tdata_reg <= 0;
|
||||
m_axis_tvalid_reg <= 0;
|
||||
rxd_reg <= 1;
|
||||
prescale_reg <= 0;
|
||||
bit_cnt <= 0;
|
||||
busy_reg <= 0;
|
||||
overrun_error_reg <= 0;
|
||||
frame_error_reg <= 0;
|
||||
end else begin
|
||||
rxd_reg <= rxd;
|
||||
overrun_error_reg <= 0;
|
||||
frame_error_reg <= 0;
|
||||
|
||||
if (m_axis_tvalid && m_axis_tready) begin
|
||||
m_axis_tvalid_reg <= 0;
|
||||
end
|
||||
|
||||
if (prescale_reg > 0) begin
|
||||
prescale_reg <= prescale_reg - 1;
|
||||
end else if (bit_cnt > 0) begin
|
||||
if (bit_cnt > DATA_WIDTH+1) begin
|
||||
if (!rxd_reg) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
end else begin
|
||||
bit_cnt <= 0;
|
||||
prescale_reg <= 0;
|
||||
end
|
||||
end else if (bit_cnt > 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
|
||||
end else if (bit_cnt == 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
if (rxd_reg) begin
|
||||
m_axis_tdata_reg <= data_reg;
|
||||
m_axis_tvalid_reg <= 1;
|
||||
overrun_error_reg <= m_axis_tvalid_reg;
|
||||
end else begin
|
||||
frame_error_reg <= 1;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
busy_reg <= 0;
|
||||
if (!rxd_reg) begin
|
||||
prescale_reg <= (prescale << 2)-2;
|
||||
bit_cnt <= DATA_WIDTH+2;
|
||||
data_reg <= 0;
|
||||
busy_reg <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream UART
|
||||
*/
|
||||
module uart_tx #
|
||||
(
|
||||
parameter DATA_WIDTH = 8
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI input
|
||||
*/
|
||||
input wire [DATA_WIDTH-1:0] s_axis_tdata,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
output wire txd,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [15:0] prescale
|
||||
);
|
||||
|
||||
reg s_axis_tready_reg = 0;
|
||||
|
||||
reg txd_reg = 1;
|
||||
|
||||
reg busy_reg = 0;
|
||||
|
||||
reg [DATA_WIDTH:0] data_reg = 0;
|
||||
reg [18:0] prescale_reg = 0;
|
||||
reg [3:0] bit_cnt = 0;
|
||||
|
||||
assign s_axis_tready = s_axis_tready_reg;
|
||||
assign txd = txd_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
s_axis_tready_reg <= 0;
|
||||
txd_reg <= 1;
|
||||
prescale_reg <= 0;
|
||||
bit_cnt <= 0;
|
||||
busy_reg <= 0;
|
||||
end else begin
|
||||
if (prescale_reg > 0) begin
|
||||
s_axis_tready_reg <= 0;
|
||||
prescale_reg <= prescale_reg - 1;
|
||||
end else if (bit_cnt == 0) begin
|
||||
s_axis_tready_reg <= 1;
|
||||
busy_reg <= 0;
|
||||
|
||||
if (s_axis_tvalid) begin
|
||||
s_axis_tready_reg <= !s_axis_tready_reg;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
bit_cnt <= DATA_WIDTH+1;
|
||||
data_reg <= {1'b1, s_axis_tdata};
|
||||
txd_reg <= 0;
|
||||
busy_reg <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (bit_cnt > 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
{data_reg, txd_reg} <= {1'b0, data_reg};
|
||||
end else if (bit_cnt == 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3);
|
||||
txd_reg <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue