add sechzig_mx2 demo project
This commit is contained in:
AngeloJacobo
parent
a99066a556
commit
6c937879e1
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PROJECT = sechzig_mx2_ddr3
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FAMILY = artix7
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PART = xc7a35tftg256-2
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CHIPDB = ${ARTIX7_CHIPDB}
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ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
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#############################################################################################
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NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
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NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
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PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
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DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
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SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
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CHIPDB ?= ./
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ifeq ($(CHIPDB),)
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CHIPDB = ./
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endif
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PYPY3 ?= pypy3
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TOP ?= ${PROJECT}
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TOP_MODULE ?= ${TOP}
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TOP_VERILOG ?= ${TOP}.v
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PNR_DEBUG ?= # --verbose --debug
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BOARD ?= UNKNOWN
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JTAG_LINK ?= --board ${BOARD}
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XDC ?= ${PROJECT}.xdc
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.PHONY: all
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all: ${PROJECT}.bit
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.PHONY: program
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program: ${PROJECT}.bit
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openFPGALoader ${JTAG_LINK} --bitstream $<
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${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
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yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
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# The chip database only needs to be generated once
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# that is why we don't clean it with make clean
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${CHIPDB}/${DBPART}.bin:
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${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
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bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
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rm -f ${DBPART}.bba
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${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
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nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
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${PROJECT}.frames: ${PROJECT}.fasm
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fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
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${PROJECT}.bit: ${PROJECT}.frames
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xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
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.PHONY: clean
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clean:
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@rm -f *.frames
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@rm -f *.fasm
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@rm -f *.json
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@rm -f *.bin
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@rm -f *.bba
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.PHONY: pnrclean
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pnrclean:
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rm *.fasm *.frames *.bit
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@ -0,0 +1,66 @@
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`timescale 1ps/1ps
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module clk_wiz
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(
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input clk_in1,
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output clk_out1,
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output clk_out2,
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output clk_out3,
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output clk_out4,
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input reset,
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output locked
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);
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wire clk_out1_clk_wiz_0;
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wire clk_out2_clk_wiz_0;
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wire clk_out3_clk_wiz_0;
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wire clk_out4_clk_wiz_0;
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wire clkfbout;
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PLLE2_ADV
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#(.BANDWIDTH ("OPTIMIZED"),
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.COMPENSATION ("INTERNAL"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT (20), // 50 MHz * 20 = 1000 MHz
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.CLKFBOUT_PHASE (0.000),
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.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
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.CLKOUT2_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
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.CLKOUT3_PHASE (90.000),
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKIN1_PERIOD (20.000) // 50 MHz input
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)
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plle2_adv_inst
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(
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.CLKFBOUT (clkfbout),
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.CLKOUT0 (clk_out1_clk_wiz_0),
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.CLKOUT1 (clk_out2_clk_wiz_0),
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.CLKOUT2 (clk_out3_clk_wiz_0),
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.CLKOUT3 (clk_out4_clk_wiz_0),
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.CLKFBIN (clkfbout),
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.CLKIN1 (clk_in1),
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.LOCKED (locked),
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.RST (reset)
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);
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BUFG clkout1_buf
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(.O (clk_out1),
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.I (clk_out1_clk_wiz_0));
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BUFG clkout2_buf
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(.O (clk_out2),
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.I (clk_out2_clk_wiz_0));
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BUFG clkout3_buf
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(.O (clk_out3),
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.I (clk_out3_clk_wiz_0));
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BUFG clkout4_buf
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(.O (clk_out4),
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.I (clk_out4_clk_wiz_0));
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endmodule
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@ -0,0 +1,216 @@
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: sechzig_mx2_ddr3.v
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// Project: UberDDR3 - An Open Source DDR3 Controller
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//
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// Purpose: Example demo of UberDDR3 for Machdyne Sechzig MX2 (xc7a35tftg256-2). Mechanism:
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// - two LEDs will light up once UberDDR3 is done calibrating
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// - if UART (9600 Baud Rate)receives small letter ASCII (a-z), this value will be written to DDR3
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// - if UART receives capital letter ASCII (A-Z), the small letter equivalent will be retrieved from DDR3 by doing
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// - a read request, once read data is available this will be sent to UART to be streamed out.
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// THUS:
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// - Sendng "abcdefg" to the UART terminal will store that small latter to DDR3
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// - Then sending "ABCDEFG" to the UART terminal will return the small letter equivalent: "abcdefg"
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//
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// Engineer: Angelo C. Jacobo
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2023-2024 Angelo Jacobo
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// Copyright (C) 2024 Lone Dynamics Corporation
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module sechzig_mx2_ddr3
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(
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input wire clk50,
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// DDR3 I/O Interface
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output wire ddr3_clk_p, ddr3_clk_n,
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output wire ddr3_reset_n,
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output wire ddr3_cke, // CKE
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//output wire ddr3_cs_n, // no chip select signal
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output wire ddr3_ras_n, // RAS#
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output wire ddr3_cas_n, // CAS#
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output wire ddr3_we_n, // WE#
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output wire[14-1:0] ddr3_addr,
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output wire[3-1:0] ddr3_ba,
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inout wire[16-1:0] ddr3_dq,
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inout wire[2-1:0] ddr3_dqs_p, ddr3_dqs_n,
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output wire[2-1:0] ddr3_dm,
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output wire ddr3_odt, // on-die termination
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// UART line
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input wire rx,
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output wire tx,
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//Debug LEDs
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output wire led
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);
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wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
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wire m_axis_tvalid;
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wire rx_empty;
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wire tx_full;
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wire o_wb_ack;
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wire[7:0] o_wb_data;
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wire o_aux;
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wire[7:0] rd_data;
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wire o_wb_stall;
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reg i_wb_stb = 0, i_wb_we;
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wire[63:0] o_debug1;
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reg[7:0] i_wb_data;
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reg[7:0] i_wb_addr;
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// o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
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assign led = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
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always @(posedge i_controller_clk) begin
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begin
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i_wb_stb <= 0;
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i_wb_we <= 0;
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i_wb_addr <= 0;
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i_wb_data <= 0;
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if(!o_wb_stall && m_axis_tvalid) begin
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if(rd_data >= 97 && rd_data <= 122) begin //write to DDR3 if ASCII is small letter
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i_wb_stb <= 1;
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i_wb_we <= 1;
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i_wb_addr <= ~rd_data ;
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i_wb_data <= rd_data;
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end
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else if(rd_data >= 65 && rd_data <= 90) begin //read from DDR3 if ASCII is capital letter
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i_wb_stb <= 1; //make request
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i_wb_we <= 0; //read
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i_wb_addr <= ~(rd_data + 8'd32);
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end
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end
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end
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end
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reg i_rst_n = 1;
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(* mark_debug = "true" *) wire clk_locked;
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clk_wiz clk_wiz_inst
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(
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// Clock out ports
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.clk_out1(i_controller_clk), //83.333 Mhz
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.clk_out2(i_ddr3_clk), // 333.333 MHz
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.clk_out3(i_ref_clk), //200MHz
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.clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90degree shift
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// Status and control signals
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.reset(!i_rst_n),
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.locked(clk_locked),
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// Clock in ports
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.clk_in1(clk50)
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);
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// UART TX/RXmodule from https://github.com/ben-marshall/uart
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uart_tx #(
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.BIT_RATE(9600),
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.CLK_HZ(83_333_333),
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.PAYLOAD_BITS(8),
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.STOP_BITS(1)
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) uart_tx_inst (
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.clk(i_controller_clk), // Top level system clock input.
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.resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
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.uart_txd(tx), // UART transmit pin.
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.uart_tx_busy(), // Module busy sending previous item.
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.uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
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.uart_tx_data(o_wb_data) // The data to be sent
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);
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uart_rx #(
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.BIT_RATE(9600),
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.CLK_HZ(83_333_333),
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.PAYLOAD_BITS(8),
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.STOP_BITS(1)
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) uart_rx_inst (
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.clk(i_controller_clk), // Top level system clock input.
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.resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
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.uart_rxd(rx), // UART Recieve pin.
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.uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
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.uart_rx_break(), // Did we get a BREAK message?
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.uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
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.uart_rx_data(rd_data) // The recieved data.
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);
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// DDR3 Controller
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ddr3_top #(
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.CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ROW_BITS(14), //width of row address
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.COL_BITS(10), //width of column address
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.BA_BITS(3), //width of bank address
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.BYTE_LANES(2), //number of DDR3 modules to be controlled
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.AUX_WIDTH(4), //width of aux line (must be >= 4)
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.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
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.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
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.MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
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.SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed
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) ddr3_top_inst
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(
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//clock and reset
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
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.i_ref_clk(i_ref_clk),
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.i_ddr3_clk_90(i_ddr3_clk_90),
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.i_rst_n(i_rst_n && clk_locked),
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// Wishbone inputs
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.i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(i_wb_stb), //request a transfer
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.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
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.i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(o_wb_ack), //1 = read/write request has completed
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.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(o_aux),
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// Wishbone 2 (PHY) inputs
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.i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb2_stb(), //request a transfer
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.i_wb2_we(), //write-enable (1 = write, 0 = read)
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.i_wb2_addr(), //burst-addressable {row,bank,col}
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.i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb2_sel(), //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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.o_wb2_stall(), //1 = busy, cannot accept requests
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.o_wb2_ack(), //1 = read/write request has completed
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.o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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// PHY Interface (to be added later)
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// DDR3 I/O Interface
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.o_ddr3_clk_p(ddr3_clk_p),
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.o_ddr3_clk_n(ddr3_clk_n),
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.o_ddr3_reset_n(ddr3_reset_n),
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.o_ddr3_cke(ddr3_cke), // CKE
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.o_ddr3_cs_n(), // chip select signal (controls rank 1 only)
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.o_ddr3_ras_n(ddr3_ras_n), // RAS#
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.o_ddr3_cas_n(ddr3_cas_n), // CAS#
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.o_ddr3_we_n(ddr3_we_n), // WE#
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.o_ddr3_addr(ddr3_addr),
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.o_ddr3_ba_addr(ddr3_ba),
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.io_ddr3_dq(ddr3_dq),
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.io_ddr3_dqs(ddr3_dqs_p),
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.io_ddr3_dqs_n(ddr3_dqs_n),
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.o_ddr3_dm(ddr3_dm),
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.o_ddr3_odt(ddr3_odt), // on-die termination
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.o_debug1(o_debug1),
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.o_debug2(),
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.o_debug3()
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);
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endmodule
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@ -0,0 +1,276 @@
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################################################################################
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# IO constraints
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################################################################################
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# clk48:0
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set_property LOC F5 [get_ports {clk48}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk48}]
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# clk50:0
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set_property LOC D4 [get_ports {clk50}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk50}]
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# led
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set_property LOC R16 [get_ports {led}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led}]
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# led (n/c)
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set_property LOC T14 [get_ports {led[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
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# serial:0.tx
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set_property LOC L2 [get_ports {tx}]
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set_property IOSTANDARD LVCMOS33 [get_ports {tx}]
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# serial:0.rx
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set_property LOC L3 [get_ports {rx}]
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set_property IOSTANDARD LVCMOS33 [get_ports {rx}]
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# ddr3:0.a
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set_property LOC F12 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
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# ddr3:0.a
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set_property LOC D15 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
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# ddr3:0.a
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set_property LOC J15 [get_ports {ddr3_addr[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC E16 [get_ports {ddr3_addr[3]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC G11 [get_ports {ddr3_addr[4]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC F15 [get_ports {ddr3_addr[5]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC H13 [get_ports {ddr3_addr[6]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC G15 [get_ports {ddr3_addr[7]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC H12 [get_ports {ddr3_addr[8]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC H16 [get_ports {ddr3_addr[9]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC H11 [get_ports {ddr3_addr[10]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC H14 [get_ports {ddr3_addr[11]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC E12 [get_ports {ddr3_addr[12]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC G16 [get_ports {ddr3_addr[13]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
|
||||
|
||||
# ddr3:0.a
|
||||
set_property LOC J16 [get_ports {ddr3_addr[14]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[14]}]
|
||||
|
||||
# ddr3:0.ba
|
||||
set_property LOC E15 [get_ports {ddr3_ba[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
|
||||
|
||||
# ddr3:0.ba
|
||||
set_property LOC D11 [get_ports {ddr3_ba[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
|
||||
|
||||
# ddr3:0.ba
|
||||
set_property LOC F13 [get_ports {ddr3_ba[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
|
||||
|
||||
# ddr3:0.ras_n
|
||||
set_property LOC D14 [get_ports {ddr3_ras_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ras_n}]
|
||||
|
||||
# ddr3:0.cas_n
|
||||
set_property LOC E13 [get_ports {ddr3_cas_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cas_n}]
|
||||
|
||||
# ddr3:0.we_n
|
||||
set_property LOC G12 [get_ports {ddr3_we_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_we_n}]
|
||||
|
||||
# ddr3:0.dm
|
||||
set_property LOC A13 [get_ports {ddr3_dm[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
|
||||
|
||||
# ddr3:0.dm
|
||||
set_property LOC D9 [get_ports {ddr3_dm[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC A14 [get_ports {ddr3_dq[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[0]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC C12 [get_ports {ddr3_dq[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[1]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC B14 [get_ports {ddr3_dq[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[2]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC D13 [get_ports {ddr3_dq[3]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[3]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC B16 [get_ports {ddr3_dq[4]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[4]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC C11 [get_ports {ddr3_dq[5]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[5]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC C16 [get_ports {ddr3_dq[6]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[6]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC C14 [get_ports {ddr3_dq[7]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[7]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC A9 [get_ports {ddr3_dq[8]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[8]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC B10 [get_ports {ddr3_dq[9]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[9]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC C8 [get_ports {ddr3_dq[10]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[10]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC B12 [get_ports {ddr3_dq[11]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[11]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC A8 [get_ports {ddr3_dq[12]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[12]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC A12 [get_ports {ddr3_dq[13]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[13]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC C9 [get_ports {ddr3_dq[14]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[14]}]
|
||||
|
||||
# ddr3:0.dq
|
||||
set_property LOC B11 [get_ports {ddr3_dq[15]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dq[15]}]
|
||||
|
||||
# ddr3:0.dqs_p
|
||||
set_property LOC B15 [get_ports {ddr3_dqs_p[0]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dqs_p[0]}]
|
||||
|
||||
# ddr3:0.dqs_p
|
||||
set_property LOC B9 [get_ports {ddr3_dqs_p[1]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dqs_p[1]}]
|
||||
|
||||
# ddr3:0.dqs_n
|
||||
set_property LOC A15 [get_ports {ddr3_dqs_n[0]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dqs_n[0]}]
|
||||
|
||||
# ddr3:0.dqs_n
|
||||
set_property LOC A10 [get_ports {ddr3_dqs_n[1]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_60 [get_ports {ddr3_dqs_n[1]}]
|
||||
|
||||
# ddr3:0.clk_p
|
||||
set_property LOC G14 [get_ports {ddr3_clk_p}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_clk_p}]
|
||||
|
||||
# ddr3:0.clk_n
|
||||
set_property LOC F14 [get_ports {ddr3_clk_n}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_clk_n}]
|
||||
|
||||
# ddr3:0.cke
|
||||
set_property LOC E11 [get_ports {ddr3_cke}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke}]
|
||||
|
||||
# ddr3:0.odt
|
||||
set_property LOC D16 [get_ports {ddr3_odt}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt}]
|
||||
|
||||
# ddr3:0.reset_n
|
||||
set_property LOC M16 [get_ports {ddr3_reset_n}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {ddr3_reset_n}]
|
||||
|
||||
################################################################################
|
||||
# Design constraints
|
||||
################################################################################
|
||||
|
||||
# set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
# set_property INTERNAL_VREF 0.675 [get_iobanks 15]
|
||||
|
||||
################################################################################
|
||||
# Clock constraints
|
||||
################################################################################
|
||||
|
||||
|
||||
# create_clock -name clk48 -period 20.833 [get_ports clk48]
|
||||
|
||||
# create_clock -name clk50 -period 20.0 [get_ports clk50]
|
||||
|
||||
# create_clock -name eth_rx_clk -period 20.0 [get_nets eth_rx_clk]
|
||||
|
||||
# create_clock -name eth_tx_clk -period 20.0 [get_nets eth_tx_clk]
|
||||
|
||||
# set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
|
||||
|
||||
# set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
# set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
# ################################################################################
|
||||
# # False path constraints
|
||||
# ################################################################################
|
||||
|
||||
|
||||
# set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
|
||||
|
||||
# set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
# set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,207 @@
|
|||
|
||||
//
|
||||
// Module: uart_rx
|
||||
//
|
||||
// Notes:
|
||||
// - UART reciever module.
|
||||
//
|
||||
|
||||
module uart_rx(
|
||||
input wire clk , // Top level system clock input.
|
||||
input wire resetn , // Asynchronous active low reset.
|
||||
input wire uart_rxd , // UART Recieve pin.
|
||||
input wire uart_rx_en , // Recieve enable
|
||||
output wire uart_rx_break, // Did we get a BREAK message?
|
||||
output wire uart_rx_valid, // Valid data recieved and available.
|
||||
output reg [PAYLOAD_BITS-1:0] uart_rx_data // The recieved data.
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// External parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Input bit rate of the UART line.
|
||||
parameter BIT_RATE = 9600; // bits / sec
|
||||
localparam BIT_P = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
|
||||
|
||||
//
|
||||
// Clock frequency in hertz.
|
||||
parameter CLK_HZ = 50_000_000;
|
||||
localparam CLK_P = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
|
||||
|
||||
//
|
||||
// Number of data bits recieved per UART packet.
|
||||
parameter PAYLOAD_BITS = 8;
|
||||
|
||||
//
|
||||
// Number of stop bits indicating the end of a packet.
|
||||
parameter STOP_BITS = 1;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Number of clock cycles per uart bit.
|
||||
localparam CYCLES_PER_BIT = BIT_P / CLK_P;
|
||||
|
||||
//
|
||||
// Size of the registers which store sample counts and bit durations.
|
||||
localparam COUNT_REG_LEN = 1+$clog2(CYCLES_PER_BIT);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal registers.
|
||||
//
|
||||
|
||||
//
|
||||
// Internally latched value of the uart_rxd line. Helps break long timing
|
||||
// paths from input pins into the logic.
|
||||
reg rxd_reg;
|
||||
reg rxd_reg_0;
|
||||
|
||||
//
|
||||
// Storage for the recieved serial data.
|
||||
reg [PAYLOAD_BITS-1:0] recieved_data;
|
||||
|
||||
//
|
||||
// Counter for the number of cycles over a packet bit.
|
||||
reg [COUNT_REG_LEN-1:0] cycle_counter;
|
||||
|
||||
//
|
||||
// Counter for the number of recieved bits of the packet.
|
||||
reg [3:0] bit_counter;
|
||||
|
||||
//
|
||||
// Sample of the UART input line whenever we are in the middle of a bit frame.
|
||||
reg bit_sample;
|
||||
|
||||
//
|
||||
// Current and next states of the internal FSM.
|
||||
reg [2:0] fsm_state;
|
||||
reg [2:0] n_fsm_state;
|
||||
|
||||
localparam FSM_IDLE = 0;
|
||||
localparam FSM_START= 1;
|
||||
localparam FSM_RECV = 2;
|
||||
localparam FSM_STOP = 3;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Output assignment
|
||||
//
|
||||
|
||||
assign uart_rx_break = uart_rx_valid && ~|recieved_data;
|
||||
assign uart_rx_valid = fsm_state == FSM_STOP && n_fsm_state == FSM_IDLE;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(!resetn) begin
|
||||
uart_rx_data <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if (fsm_state == FSM_STOP) begin
|
||||
uart_rx_data <= recieved_data;
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// FSM next state selection.
|
||||
//
|
||||
|
||||
wire next_bit = cycle_counter == CYCLES_PER_BIT ||
|
||||
fsm_state == FSM_STOP &&
|
||||
cycle_counter == CYCLES_PER_BIT/2;
|
||||
wire payload_done = bit_counter == PAYLOAD_BITS ;
|
||||
|
||||
//
|
||||
// Handle picking the next state.
|
||||
always @(*) begin : p_n_fsm_state
|
||||
case(fsm_state)
|
||||
FSM_IDLE : n_fsm_state = rxd_reg ? FSM_IDLE : FSM_START;
|
||||
FSM_START: n_fsm_state = next_bit ? FSM_RECV : FSM_START;
|
||||
FSM_RECV : n_fsm_state = payload_done ? FSM_STOP : FSM_RECV ;
|
||||
FSM_STOP : n_fsm_state = next_bit ? FSM_IDLE : FSM_STOP ;
|
||||
default : n_fsm_state = FSM_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal register setting and re-setting.
|
||||
//
|
||||
|
||||
//
|
||||
// Handle updates to the recieved data register.
|
||||
integer i = 0;
|
||||
always @(posedge clk) begin : p_recieved_data
|
||||
if(!resetn) begin
|
||||
recieved_data <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if(fsm_state == FSM_IDLE ) begin
|
||||
recieved_data <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if(fsm_state == FSM_RECV && next_bit ) begin
|
||||
recieved_data[PAYLOAD_BITS-1] <= bit_sample;
|
||||
for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
|
||||
recieved_data[i] <= recieved_data[i+1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
// Increments the bit counter when recieving.
|
||||
always @(posedge clk) begin : p_bit_counter
|
||||
if(!resetn) begin
|
||||
bit_counter <= 4'b0;
|
||||
end else if(fsm_state != FSM_RECV) begin
|
||||
bit_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_RECV && next_bit) begin
|
||||
bit_counter <= bit_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
// Sample the recieved bit when in the middle of a bit frame.
|
||||
always @(posedge clk) begin : p_bit_sample
|
||||
if(!resetn) begin
|
||||
bit_sample <= 1'b0;
|
||||
end else if (cycle_counter == CYCLES_PER_BIT/2) begin
|
||||
bit_sample <= rxd_reg;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Increments the cycle counter when recieving.
|
||||
always @(posedge clk) begin : p_cycle_counter
|
||||
if(!resetn) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(next_bit) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_START ||
|
||||
fsm_state == FSM_RECV ||
|
||||
fsm_state == FSM_STOP ) begin
|
||||
cycle_counter <= cycle_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Progresses the next FSM state.
|
||||
always @(posedge clk) begin : p_fsm_state
|
||||
if(!resetn) begin
|
||||
fsm_state <= FSM_IDLE;
|
||||
end else begin
|
||||
fsm_state <= n_fsm_state;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Responsible for updating the internal value of the rxd_reg.
|
||||
always @(posedge clk) begin : p_rxd_reg
|
||||
if(!resetn) begin
|
||||
rxd_reg <= 1'b1;
|
||||
rxd_reg_0 <= 1'b1;
|
||||
end else if(uart_rx_en) begin
|
||||
rxd_reg <= rxd_reg_0;
|
||||
rxd_reg_0 <= uart_rxd;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
|
||||
|
||||
//
|
||||
// Module: uart_tx
|
||||
//
|
||||
// Notes:
|
||||
// - UART transmitter module.
|
||||
//
|
||||
|
||||
module uart_tx(
|
||||
input wire clk , // Top level system clock input.
|
||||
input wire resetn , // Asynchronous active low reset.
|
||||
output wire uart_txd , // UART transmit pin.
|
||||
output wire uart_tx_busy, // Module busy sending previous item.
|
||||
input wire uart_tx_en , // Send the data on uart_tx_data
|
||||
input wire [PAYLOAD_BITS-1:0] uart_tx_data // The data to be sent
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// External parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Input bit rate of the UART line.
|
||||
parameter BIT_RATE = 9600; // bits / sec
|
||||
localparam BIT_P = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
|
||||
|
||||
//
|
||||
// Clock frequency in hertz.
|
||||
parameter CLK_HZ = 50_000_000;
|
||||
localparam CLK_P = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
|
||||
|
||||
//
|
||||
// Number of data bits recieved per UART packet.
|
||||
parameter PAYLOAD_BITS = 8;
|
||||
|
||||
//
|
||||
// Number of stop bits indicating the end of a packet.
|
||||
parameter STOP_BITS = 1;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Number of clock cycles per uart bit.
|
||||
localparam CYCLES_PER_BIT = BIT_P / CLK_P;
|
||||
|
||||
//
|
||||
// Size of the registers which store sample counts and bit durations.
|
||||
localparam COUNT_REG_LEN = 1+$clog2(CYCLES_PER_BIT);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal registers.
|
||||
//
|
||||
|
||||
//
|
||||
// Internally latched value of the uart_txd line. Helps break long timing
|
||||
// paths from the logic to the output pins.
|
||||
reg txd_reg;
|
||||
|
||||
//
|
||||
// Storage for the serial data to be sent.
|
||||
reg [PAYLOAD_BITS-1:0] data_to_send;
|
||||
|
||||
//
|
||||
// Counter for the number of cycles over a packet bit.
|
||||
reg [COUNT_REG_LEN-1:0] cycle_counter;
|
||||
|
||||
//
|
||||
// Counter for the number of sent bits of the packet.
|
||||
reg [3:0] bit_counter;
|
||||
|
||||
//
|
||||
// Current and next states of the internal FSM.
|
||||
reg [2:0] fsm_state;
|
||||
reg [2:0] n_fsm_state;
|
||||
|
||||
localparam FSM_IDLE = 0;
|
||||
localparam FSM_START= 1;
|
||||
localparam FSM_SEND = 2;
|
||||
localparam FSM_STOP = 3;
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// FSM next state selection.
|
||||
//
|
||||
|
||||
assign uart_tx_busy = fsm_state != FSM_IDLE;
|
||||
assign uart_txd = txd_reg;
|
||||
|
||||
wire next_bit = cycle_counter == CYCLES_PER_BIT;
|
||||
wire payload_done = bit_counter == PAYLOAD_BITS ;
|
||||
wire stop_done = bit_counter == STOP_BITS && fsm_state == FSM_STOP;
|
||||
|
||||
//
|
||||
// Handle picking the next state.
|
||||
always @(*) begin : p_n_fsm_state
|
||||
case(fsm_state)
|
||||
FSM_IDLE : n_fsm_state = uart_tx_en ? FSM_START: FSM_IDLE ;
|
||||
FSM_START: n_fsm_state = next_bit ? FSM_SEND : FSM_START;
|
||||
FSM_SEND : n_fsm_state = payload_done ? FSM_STOP : FSM_SEND ;
|
||||
FSM_STOP : n_fsm_state = stop_done ? FSM_IDLE : FSM_STOP ;
|
||||
default : n_fsm_state = FSM_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal register setting and re-setting.
|
||||
//
|
||||
|
||||
//
|
||||
// Handle updates to the sent data register.
|
||||
integer i = 0;
|
||||
always @(posedge clk) begin : p_data_to_send
|
||||
if(!resetn) begin
|
||||
data_to_send <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if(fsm_state == FSM_IDLE && uart_tx_en) begin
|
||||
data_to_send <= uart_tx_data;
|
||||
end else if(fsm_state == FSM_SEND && next_bit ) begin
|
||||
for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
|
||||
data_to_send[i] <= data_to_send[i+1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Increments the bit counter each time a new bit frame is sent.
|
||||
always @(posedge clk) begin : p_bit_counter
|
||||
if(!resetn) begin
|
||||
bit_counter <= 4'b0;
|
||||
end else if(fsm_state != FSM_SEND && fsm_state != FSM_STOP) begin
|
||||
bit_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_SEND && n_fsm_state == FSM_STOP) begin
|
||||
bit_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_STOP&& next_bit) begin
|
||||
bit_counter <= bit_counter + 1'b1;
|
||||
end else if(fsm_state == FSM_SEND && next_bit) begin
|
||||
bit_counter <= bit_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Increments the cycle counter when sending.
|
||||
always @(posedge clk) begin : p_cycle_counter
|
||||
if(!resetn) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(next_bit) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_START ||
|
||||
fsm_state == FSM_SEND ||
|
||||
fsm_state == FSM_STOP ) begin
|
||||
cycle_counter <= cycle_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Progresses the next FSM state.
|
||||
always @(posedge clk) begin : p_fsm_state
|
||||
if(!resetn) begin
|
||||
fsm_state <= FSM_IDLE;
|
||||
end else begin
|
||||
fsm_state <= n_fsm_state;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Responsible for updating the internal value of the txd_reg.
|
||||
always @(posedge clk) begin : p_txd_reg
|
||||
if(!resetn) begin
|
||||
txd_reg <= 1'b1;
|
||||
end else if(fsm_state == FSM_IDLE) begin
|
||||
txd_reg <= 1'b1;
|
||||
end else if(fsm_state == FSM_START) begin
|
||||
txd_reg <= 1'b0;
|
||||
end else if(fsm_state == FSM_SEND) begin
|
||||
txd_reg <= data_to_send[0];
|
||||
end else if(fsm_state == FSM_STOP) begin
|
||||
txd_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue