add makefile for openxc7 run (WORKING)
This commit is contained in:
AngeloJacobo
parent
d3a0204ab5
commit
a99066a556
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@ -0,0 +1,70 @@
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PROJECT = ax7103_ddr3
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FAMILY = artix7
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PART = xc7a100tfgg484-2
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CHIPDB = ${ARTIX7_CHIPDB}
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ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
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#############################################################################################
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NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
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NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
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PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
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DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
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SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
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CHIPDB ?= ./
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ifeq ($(CHIPDB),)
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CHIPDB = ./
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endif
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PYPY3 ?= pypy3
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TOP ?= ${PROJECT}
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TOP_MODULE ?= ${TOP}
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TOP_VERILOG ?= ${TOP}.v
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PNR_DEBUG ?= # --verbose --debug
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BOARD ?= UNKNOWN
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JTAG_LINK ?= --board ${BOARD}
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XDC ?= ${PROJECT}.xdc
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.PHONY: all
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all: ${PROJECT}.bit
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.PHONY: program
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program: ${PROJECT}.bit
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openFPGALoader ${JTAG_LINK} --bitstream $<
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${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
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yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
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# The chip database only needs to be generated once
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# that is why we don't clean it with make clean
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${CHIPDB}/${DBPART}.bin:
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${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
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bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
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rm -f ${DBPART}.bba
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${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
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nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
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${PROJECT}.frames: ${PROJECT}.fasm
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fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
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${PROJECT}.bit: ${PROJECT}.frames
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xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
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.PHONY: clean
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clean:
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@rm -f *.bit
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@rm -f *.frames
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@rm -f *.fasm
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@rm -f *.json
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@rm -f *.bin
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@rm -f *.bba
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.PHONY: pnrclean
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pnrclean:
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rm *.fasm *.frames *.bit
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Binary file not shown.
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@ -3,7 +3,7 @@
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// Filename: ax7103_ddr3.v
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// Project: UberDDR3 - An Open Source DDR3 Controller
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//
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// Purpose: Example demo of UberDDR3 for ALINX AX7103 (c7a100tfgg484-2). Mechanism:
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// Purpose: Example demo of UberDDR3 for ALINX AX7103 (xc7a100tfgg484-2). Mechanism:
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// - four LEDs will light up once UberDDR3 is done calibrating
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// - if UART (9600 Baud Rate)receives small letter ASCII (a-z), this value will be written to DDR3
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// - if UART receives capital letter ASCII (A-Z), the small letter equivalent will be retrieved from DDR3 by doing
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@ -41,10 +41,10 @@
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input wire sys_clk_n, //system clock negative on board
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input wire i_rst_n,
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// DDR3 I/O Interface
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output wire[0:0] ddr3_ck_p, ddr3_ck_n,
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output wire ddr3_ck_p, ddr3_ck_n,
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output wire ddr3_reset_n,
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output wire[0:0] ddr3_cke,
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output wire[0:0] ddr3_cs_n,
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output wire ddr3_cke,
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output wire ddr3_cs_n,
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output wire ddr3_ras_n,
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output wire ddr3_cas_n,
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output wire ddr3_we_n,
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@ -53,7 +53,7 @@
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inout wire[32-1:0] ddr3_dq,
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inout wire[4-1:0] ddr3_dqs_p, ddr3_dqs_n,
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output wire[4-1:0] ddr3_dm,
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output wire[0:0] ddr3_odt,
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output wire ddr3_odt,
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// UART line
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input wire rx,
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output wire tx,
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@ -83,7 +83,7 @@
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reg[7:0] i_wb_data;
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reg[7:0] i_wb_addr;
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// o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
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assign led[0] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
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assign led[0] = !(o_debug1[4:0] != 23); //light up if not at DONE_CALIBRATE
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assign led[1] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
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assign led[2] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
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assign led[3] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
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@ -114,10 +114,10 @@
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clk_wiz clk_wiz_inst
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(
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// Clock out ports
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.clk_out1(i_controller_clk), //100 Mhz
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.clk_out2(i_ddr3_clk), // 400 MHz
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.clk_out1(i_controller_clk), //83.333 Mhz
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.clk_out2(i_ddr3_clk), // 333.333 MHz
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.clk_out3(i_ref_clk), // 200 MHz
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.clk_out4(i_ddr3_clk_90), // 400 MHz 90-degree
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.clk_out4(i_ddr3_clk_90), // 333.333 MHz 90-degree
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// Status and control signals
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.reset(!i_rst_n),
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.locked(clk_locked),
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@ -125,26 +125,56 @@
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.clk_in1(sys_clk_200MHz)
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);
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// UART module from https://github.com/alexforencich/verilog-uart
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uart #(.DATA_WIDTH(8)) uart_m
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(
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.clk(i_controller_clk),
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.rst(!i_rst_n),
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.s_axis_tdata(o_wb_data),
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.s_axis_tvalid(o_wb_ack),
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.s_axis_tready(),
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.m_axis_tdata(rd_data),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(1),
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.rxd(rx),
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.txd(tx),
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.prescale(1302) //9600 Baud Rate: 100MHz/(8*9600)
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// UART TX/RXmodule from https://github.com/ben-marshall/uart
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uart_tx #(
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.BIT_RATE(9600),
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.CLK_HZ(83_333_333),
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.PAYLOAD_BITS(8),
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.STOP_BITS(1)
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) uart_tx_inst (
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.clk(i_controller_clk), // Top level system clock input.
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.resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
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.uart_txd(tx), // UART transmit pin.
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.uart_tx_busy(), // Module busy sending previous item.
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.uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
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.uart_tx_data(o_wb_data) // The data to be sent
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);
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uart_rx #(
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.BIT_RATE(9600),
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.CLK_HZ(83_333_333),
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.PAYLOAD_BITS(8),
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.STOP_BITS(1)
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) uart_rx_inst (
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.clk(i_controller_clk), // Top level system clock input.
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.resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
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.uart_rxd(rx), // UART Recieve pin.
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.uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
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.uart_rx_break(), // Did we get a BREAK message?
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.uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
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.uart_rx_data(rd_data) // The recieved data.
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);
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// UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)
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// uart #(.DATA_WIDTH(8)) uart_m
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// (
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// .clk(i_controller_clk),
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// .rst(!i_rst_n),
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// .s_axis_tdata(o_wb_data),
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// .s_axis_tvalid(o_wb_ack),
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// .s_axis_tready(),
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// .m_axis_tdata(rd_data),
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// .m_axis_tvalid(m_axis_tvalid),
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// .m_axis_tready(1),
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// .rxd(rx),
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// .txd(tx),
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// .prescale(1085) //9600 Baud Rate (83.33MHz/(8*9600))
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// );
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// DDR3 Controller
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ddr3_top #(
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.CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ROW_BITS(15), //width of row address
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.COL_BITS(10), //width of column address
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.BA_BITS(3), //width of bank address
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@ -9,6 +9,9 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
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create_clock -period 5 [get_ports sys_clk_p]
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set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
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set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
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##############reset key define########################
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set_property PACKAGE_PIN J21 [get_ports i_rst_n]
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set_property IOSTANDARD LVCMOS33 [get_ports i_rst_n]
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@ -341,19 +344,19 @@ set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
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set_property PACKAGE_PIN W6 [get_ports {ddr3_reset_n}]
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# PadFunction: IO_L14P_T2_SRCC_34
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set_property SLEW FAST [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
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set_property PACKAGE_PIN T5 [get_ports {ddr3_cke[0]}]
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set_property SLEW FAST [get_ports {ddr3_cke}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke}]
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set_property PACKAGE_PIN T5 [get_ports {ddr3_cke}]
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# PadFunction: IO_L14N_T2_SRCC_34
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set_property SLEW FAST [get_ports {ddr3_odt[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
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set_property PACKAGE_PIN U5 [get_ports {ddr3_odt[0]}]
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set_property SLEW FAST [get_ports {ddr3_odt}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt}]
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set_property PACKAGE_PIN U5 [get_ports {ddr3_odt}]
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# PadFunction: IO_L8P_T1_34
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set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
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set_property PACKAGE_PIN AB3 [get_ports {ddr3_cs_n[0]}]
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set_property SLEW FAST [get_ports {ddr3_cs_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n}]
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set_property PACKAGE_PIN AB3 [get_ports {ddr3_cs_n}]
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# PadFunction: IO_L4N_T0_35
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set_property SLEW FAST [get_ports {ddr3_dm[0]}]
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@ -424,14 +427,14 @@ set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
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set_property PACKAGE_PIN P4 [get_ports {ddr3_dqs_n[3]}]
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# PadFunction: IO_L3P_T0_DQS_34
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set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]
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set_property PACKAGE_PIN R3 [get_ports {ddr3_ck_p[0]}]
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set_property SLEW FAST [get_ports {ddr3_ck_p}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p}]
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set_property PACKAGE_PIN R3 [get_ports {ddr3_ck_p}]
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# PadFunction: IO_L3N_T0_DQS_34
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set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
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set_property PACKAGE_PIN R2 [get_ports {ddr3_ck_n[0]}]
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set_property SLEW FAST [get_ports {ddr3_ck_n}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n}]
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set_property PACKAGE_PIN R2 [get_ports {ddr3_ck_n}]
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@ -22,18 +22,18 @@ module clk_wiz
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.COMPENSATION ("INTERNAL"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT (4), // 200 MHz * 4 = 800 MHz
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.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
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.CLKFBOUT_PHASE (0.000),
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.CLKOUT0_DIVIDE (8), // 800 MHz / 8 = 100 MHz
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.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT1_DIVIDE (2), // 800 MHz / 2 = 400 MHz
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.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT2_DIVIDE (4), // 800 MHz / 4 = 200 MHz
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.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
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.CLKOUT2_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT3_DIVIDE (2), // 800 MHz / 2 = 400 MHz
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.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
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.CLKOUT3_PHASE (90),
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKIN1_PERIOD (5.000) // 200 MHz input
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@ -1,113 +0,0 @@
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/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream UART
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*/
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module uart #
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(
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parameter DATA_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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/*
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* UART interface
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*/
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input wire rxd,
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output wire txd,
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/*
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* Status
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*/
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output wire tx_busy,
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output wire rx_busy,
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output wire rx_overrun_error,
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output wire rx_frame_error,
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/*
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* Configuration
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*/
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input wire [15:0] prescale
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);
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uart_tx #(
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.DATA_WIDTH(DATA_WIDTH)
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)
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uart_tx_inst (
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.clk(clk),
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.rst(rst),
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// axi input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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// output
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.txd(txd),
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// status
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.busy(tx_busy),
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// configuration
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.prescale(prescale)
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);
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uart_rx #(
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.DATA_WIDTH(DATA_WIDTH)
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)
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uart_rx_inst (
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.clk(clk),
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.rst(rst),
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// axi output
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
// input
|
||||
.rxd(rxd),
|
||||
// status
|
||||
.busy(rx_busy),
|
||||
.overrun_error(rx_overrun_error),
|
||||
.frame_error(rx_frame_error),
|
||||
// configuration
|
||||
.prescale(prescale)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,142 +1,207 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream UART
|
||||
*/
|
||||
module uart_rx #
|
||||
(
|
||||
parameter DATA_WIDTH = 8
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI output
|
||||
*/
|
||||
output wire [DATA_WIDTH-1:0] m_axis_tdata,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
input wire rxd,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
output wire overrun_error,
|
||||
output wire frame_error,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [15:0] prescale
|
||||
|
||||
);
|
||||
|
||||
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = 0;
|
||||
reg m_axis_tvalid_reg = 0;
|
||||
|
||||
reg rxd_reg = 1;
|
||||
|
||||
reg busy_reg = 0;
|
||||
reg overrun_error_reg = 0;
|
||||
reg frame_error_reg = 0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_reg = 0;
|
||||
reg [18:0] prescale_reg = 0;
|
||||
reg [3:0] bit_cnt = 0;
|
||||
|
||||
assign m_axis_tdata = m_axis_tdata_reg;
|
||||
assign m_axis_tvalid = m_axis_tvalid_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
assign overrun_error = overrun_error_reg;
|
||||
assign frame_error = frame_error_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
m_axis_tdata_reg <= 0;
|
||||
m_axis_tvalid_reg <= 0;
|
||||
rxd_reg <= 1;
|
||||
prescale_reg <= 0;
|
||||
bit_cnt <= 0;
|
||||
busy_reg <= 0;
|
||||
overrun_error_reg <= 0;
|
||||
frame_error_reg <= 0;
|
||||
end else begin
|
||||
rxd_reg <= rxd;
|
||||
overrun_error_reg <= 0;
|
||||
frame_error_reg <= 0;
|
||||
|
||||
if (m_axis_tvalid && m_axis_tready) begin
|
||||
m_axis_tvalid_reg <= 0;
|
||||
end
|
||||
|
||||
if (prescale_reg > 0) begin
|
||||
prescale_reg <= prescale_reg - 1;
|
||||
end else if (bit_cnt > 0) begin
|
||||
if (bit_cnt > DATA_WIDTH+1) begin
|
||||
if (!rxd_reg) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
end else begin
|
||||
bit_cnt <= 0;
|
||||
prescale_reg <= 0;
|
||||
end
|
||||
end else if (bit_cnt > 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
|
||||
end else if (bit_cnt == 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
if (rxd_reg) begin
|
||||
m_axis_tdata_reg <= data_reg;
|
||||
m_axis_tvalid_reg <= 1;
|
||||
overrun_error_reg <= m_axis_tvalid_reg;
|
||||
end else begin
|
||||
frame_error_reg <= 1;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
busy_reg <= 0;
|
||||
if (!rxd_reg) begin
|
||||
prescale_reg <= (prescale << 2)-2;
|
||||
bit_cnt <= DATA_WIDTH+2;
|
||||
data_reg <= 0;
|
||||
busy_reg <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//
|
||||
// Module: uart_rx
|
||||
//
|
||||
// Notes:
|
||||
// - UART reciever module.
|
||||
//
|
||||
|
||||
module uart_rx(
|
||||
input wire clk , // Top level system clock input.
|
||||
input wire resetn , // Asynchronous active low reset.
|
||||
input wire uart_rxd , // UART Recieve pin.
|
||||
input wire uart_rx_en , // Recieve enable
|
||||
output wire uart_rx_break, // Did we get a BREAK message?
|
||||
output wire uart_rx_valid, // Valid data recieved and available.
|
||||
output reg [PAYLOAD_BITS-1:0] uart_rx_data // The recieved data.
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// External parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Input bit rate of the UART line.
|
||||
parameter BIT_RATE = 9600; // bits / sec
|
||||
localparam BIT_P = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
|
||||
|
||||
//
|
||||
// Clock frequency in hertz.
|
||||
parameter CLK_HZ = 50_000_000;
|
||||
localparam CLK_P = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
|
||||
|
||||
//
|
||||
// Number of data bits recieved per UART packet.
|
||||
parameter PAYLOAD_BITS = 8;
|
||||
|
||||
//
|
||||
// Number of stop bits indicating the end of a packet.
|
||||
parameter STOP_BITS = 1;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Number of clock cycles per uart bit.
|
||||
localparam CYCLES_PER_BIT = BIT_P / CLK_P;
|
||||
|
||||
//
|
||||
// Size of the registers which store sample counts and bit durations.
|
||||
localparam COUNT_REG_LEN = 1+$clog2(CYCLES_PER_BIT);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal registers.
|
||||
//
|
||||
|
||||
//
|
||||
// Internally latched value of the uart_rxd line. Helps break long timing
|
||||
// paths from input pins into the logic.
|
||||
reg rxd_reg;
|
||||
reg rxd_reg_0;
|
||||
|
||||
//
|
||||
// Storage for the recieved serial data.
|
||||
reg [PAYLOAD_BITS-1:0] recieved_data;
|
||||
|
||||
//
|
||||
// Counter for the number of cycles over a packet bit.
|
||||
reg [COUNT_REG_LEN-1:0] cycle_counter;
|
||||
|
||||
//
|
||||
// Counter for the number of recieved bits of the packet.
|
||||
reg [3:0] bit_counter;
|
||||
|
||||
//
|
||||
// Sample of the UART input line whenever we are in the middle of a bit frame.
|
||||
reg bit_sample;
|
||||
|
||||
//
|
||||
// Current and next states of the internal FSM.
|
||||
reg [2:0] fsm_state;
|
||||
reg [2:0] n_fsm_state;
|
||||
|
||||
localparam FSM_IDLE = 0;
|
||||
localparam FSM_START= 1;
|
||||
localparam FSM_RECV = 2;
|
||||
localparam FSM_STOP = 3;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Output assignment
|
||||
//
|
||||
|
||||
assign uart_rx_break = uart_rx_valid && ~|recieved_data;
|
||||
assign uart_rx_valid = fsm_state == FSM_STOP && n_fsm_state == FSM_IDLE;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(!resetn) begin
|
||||
uart_rx_data <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if (fsm_state == FSM_STOP) begin
|
||||
uart_rx_data <= recieved_data;
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// FSM next state selection.
|
||||
//
|
||||
|
||||
wire next_bit = cycle_counter == CYCLES_PER_BIT ||
|
||||
fsm_state == FSM_STOP &&
|
||||
cycle_counter == CYCLES_PER_BIT/2;
|
||||
wire payload_done = bit_counter == PAYLOAD_BITS ;
|
||||
|
||||
//
|
||||
// Handle picking the next state.
|
||||
always @(*) begin : p_n_fsm_state
|
||||
case(fsm_state)
|
||||
FSM_IDLE : n_fsm_state = rxd_reg ? FSM_IDLE : FSM_START;
|
||||
FSM_START: n_fsm_state = next_bit ? FSM_RECV : FSM_START;
|
||||
FSM_RECV : n_fsm_state = payload_done ? FSM_STOP : FSM_RECV ;
|
||||
FSM_STOP : n_fsm_state = next_bit ? FSM_IDLE : FSM_STOP ;
|
||||
default : n_fsm_state = FSM_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal register setting and re-setting.
|
||||
//
|
||||
|
||||
//
|
||||
// Handle updates to the recieved data register.
|
||||
integer i = 0;
|
||||
always @(posedge clk) begin : p_recieved_data
|
||||
if(!resetn) begin
|
||||
recieved_data <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if(fsm_state == FSM_IDLE ) begin
|
||||
recieved_data <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if(fsm_state == FSM_RECV && next_bit ) begin
|
||||
recieved_data[PAYLOAD_BITS-1] <= bit_sample;
|
||||
for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
|
||||
recieved_data[i] <= recieved_data[i+1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
// Increments the bit counter when recieving.
|
||||
always @(posedge clk) begin : p_bit_counter
|
||||
if(!resetn) begin
|
||||
bit_counter <= 4'b0;
|
||||
end else if(fsm_state != FSM_RECV) begin
|
||||
bit_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_RECV && next_bit) begin
|
||||
bit_counter <= bit_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
// Sample the recieved bit when in the middle of a bit frame.
|
||||
always @(posedge clk) begin : p_bit_sample
|
||||
if(!resetn) begin
|
||||
bit_sample <= 1'b0;
|
||||
end else if (cycle_counter == CYCLES_PER_BIT/2) begin
|
||||
bit_sample <= rxd_reg;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Increments the cycle counter when recieving.
|
||||
always @(posedge clk) begin : p_cycle_counter
|
||||
if(!resetn) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(next_bit) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_START ||
|
||||
fsm_state == FSM_RECV ||
|
||||
fsm_state == FSM_STOP ) begin
|
||||
cycle_counter <= cycle_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Progresses the next FSM state.
|
||||
always @(posedge clk) begin : p_fsm_state
|
||||
if(!resetn) begin
|
||||
fsm_state <= FSM_IDLE;
|
||||
end else begin
|
||||
fsm_state <= n_fsm_state;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Responsible for updating the internal value of the rxd_reg.
|
||||
always @(posedge clk) begin : p_rxd_reg
|
||||
if(!resetn) begin
|
||||
rxd_reg <= 1'b1;
|
||||
rxd_reg_0 <= 1'b1;
|
||||
end else if(uart_rx_en) begin
|
||||
rxd_reg <= rxd_reg_0;
|
||||
rxd_reg_0 <= uart_rxd;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,115 +1,187 @@
|
|||
/*
|
||||
|
||||
Copyright (c) 2014-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream UART
|
||||
*/
|
||||
module uart_tx #
|
||||
(
|
||||
parameter DATA_WIDTH = 8
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI input
|
||||
*/
|
||||
input wire [DATA_WIDTH-1:0] s_axis_tdata,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
output wire txd,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [15:0] prescale
|
||||
);
|
||||
|
||||
reg s_axis_tready_reg = 0;
|
||||
|
||||
reg txd_reg = 1;
|
||||
|
||||
reg busy_reg = 0;
|
||||
|
||||
reg [DATA_WIDTH:0] data_reg = 0;
|
||||
reg [18:0] prescale_reg = 0;
|
||||
reg [3:0] bit_cnt = 0;
|
||||
|
||||
assign s_axis_tready = s_axis_tready_reg;
|
||||
assign txd = txd_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
s_axis_tready_reg <= 0;
|
||||
txd_reg <= 1;
|
||||
prescale_reg <= 0;
|
||||
bit_cnt <= 0;
|
||||
busy_reg <= 0;
|
||||
end else begin
|
||||
if (prescale_reg > 0) begin
|
||||
s_axis_tready_reg <= 0;
|
||||
prescale_reg <= prescale_reg - 1;
|
||||
end else if (bit_cnt == 0) begin
|
||||
s_axis_tready_reg <= 1;
|
||||
busy_reg <= 0;
|
||||
|
||||
if (s_axis_tvalid) begin
|
||||
s_axis_tready_reg <= !s_axis_tready_reg;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
bit_cnt <= DATA_WIDTH+1;
|
||||
data_reg <= {1'b1, s_axis_tdata};
|
||||
txd_reg <= 0;
|
||||
busy_reg <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (bit_cnt > 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3)-1;
|
||||
{data_reg, txd_reg} <= {1'b0, data_reg};
|
||||
end else if (bit_cnt == 1) begin
|
||||
bit_cnt <= bit_cnt - 1;
|
||||
prescale_reg <= (prescale << 3);
|
||||
txd_reg <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//
|
||||
// Module: uart_tx
|
||||
//
|
||||
// Notes:
|
||||
// - UART transmitter module.
|
||||
//
|
||||
|
||||
module uart_tx(
|
||||
input wire clk , // Top level system clock input.
|
||||
input wire resetn , // Asynchronous active low reset.
|
||||
output wire uart_txd , // UART transmit pin.
|
||||
output wire uart_tx_busy, // Module busy sending previous item.
|
||||
input wire uart_tx_en , // Send the data on uart_tx_data
|
||||
input wire [PAYLOAD_BITS-1:0] uart_tx_data // The data to be sent
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// External parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Input bit rate of the UART line.
|
||||
parameter BIT_RATE = 9600; // bits / sec
|
||||
localparam BIT_P = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
|
||||
|
||||
//
|
||||
// Clock frequency in hertz.
|
||||
parameter CLK_HZ = 50_000_000;
|
||||
localparam CLK_P = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
|
||||
|
||||
//
|
||||
// Number of data bits recieved per UART packet.
|
||||
parameter PAYLOAD_BITS = 8;
|
||||
|
||||
//
|
||||
// Number of stop bits indicating the end of a packet.
|
||||
parameter STOP_BITS = 1;
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal parameters.
|
||||
//
|
||||
|
||||
//
|
||||
// Number of clock cycles per uart bit.
|
||||
localparam CYCLES_PER_BIT = BIT_P / CLK_P;
|
||||
|
||||
//
|
||||
// Size of the registers which store sample counts and bit durations.
|
||||
localparam COUNT_REG_LEN = 1+$clog2(CYCLES_PER_BIT);
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal registers.
|
||||
//
|
||||
|
||||
//
|
||||
// Internally latched value of the uart_txd line. Helps break long timing
|
||||
// paths from the logic to the output pins.
|
||||
reg txd_reg;
|
||||
|
||||
//
|
||||
// Storage for the serial data to be sent.
|
||||
reg [PAYLOAD_BITS-1:0] data_to_send;
|
||||
|
||||
//
|
||||
// Counter for the number of cycles over a packet bit.
|
||||
reg [COUNT_REG_LEN-1:0] cycle_counter;
|
||||
|
||||
//
|
||||
// Counter for the number of sent bits of the packet.
|
||||
reg [3:0] bit_counter;
|
||||
|
||||
//
|
||||
// Current and next states of the internal FSM.
|
||||
reg [2:0] fsm_state;
|
||||
reg [2:0] n_fsm_state;
|
||||
|
||||
localparam FSM_IDLE = 0;
|
||||
localparam FSM_START= 1;
|
||||
localparam FSM_SEND = 2;
|
||||
localparam FSM_STOP = 3;
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// FSM next state selection.
|
||||
//
|
||||
|
||||
assign uart_tx_busy = fsm_state != FSM_IDLE;
|
||||
assign uart_txd = txd_reg;
|
||||
|
||||
wire next_bit = cycle_counter == CYCLES_PER_BIT;
|
||||
wire payload_done = bit_counter == PAYLOAD_BITS ;
|
||||
wire stop_done = bit_counter == STOP_BITS && fsm_state == FSM_STOP;
|
||||
|
||||
//
|
||||
// Handle picking the next state.
|
||||
always @(*) begin : p_n_fsm_state
|
||||
case(fsm_state)
|
||||
FSM_IDLE : n_fsm_state = uart_tx_en ? FSM_START: FSM_IDLE ;
|
||||
FSM_START: n_fsm_state = next_bit ? FSM_SEND : FSM_START;
|
||||
FSM_SEND : n_fsm_state = payload_done ? FSM_STOP : FSM_SEND ;
|
||||
FSM_STOP : n_fsm_state = stop_done ? FSM_IDLE : FSM_STOP ;
|
||||
default : n_fsm_state = FSM_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Internal register setting and re-setting.
|
||||
//
|
||||
|
||||
//
|
||||
// Handle updates to the sent data register.
|
||||
integer i = 0;
|
||||
always @(posedge clk) begin : p_data_to_send
|
||||
if(!resetn) begin
|
||||
data_to_send <= {PAYLOAD_BITS{1'b0}};
|
||||
end else if(fsm_state == FSM_IDLE && uart_tx_en) begin
|
||||
data_to_send <= uart_tx_data;
|
||||
end else if(fsm_state == FSM_SEND && next_bit ) begin
|
||||
for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
|
||||
data_to_send[i] <= data_to_send[i+1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Increments the bit counter each time a new bit frame is sent.
|
||||
always @(posedge clk) begin : p_bit_counter
|
||||
if(!resetn) begin
|
||||
bit_counter <= 4'b0;
|
||||
end else if(fsm_state != FSM_SEND && fsm_state != FSM_STOP) begin
|
||||
bit_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_SEND && n_fsm_state == FSM_STOP) begin
|
||||
bit_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_STOP&& next_bit) begin
|
||||
bit_counter <= bit_counter + 1'b1;
|
||||
end else if(fsm_state == FSM_SEND && next_bit) begin
|
||||
bit_counter <= bit_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Increments the cycle counter when sending.
|
||||
always @(posedge clk) begin : p_cycle_counter
|
||||
if(!resetn) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(next_bit) begin
|
||||
cycle_counter <= {COUNT_REG_LEN{1'b0}};
|
||||
end else if(fsm_state == FSM_START ||
|
||||
fsm_state == FSM_SEND ||
|
||||
fsm_state == FSM_STOP ) begin
|
||||
cycle_counter <= cycle_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Progresses the next FSM state.
|
||||
always @(posedge clk) begin : p_fsm_state
|
||||
if(!resetn) begin
|
||||
fsm_state <= FSM_IDLE;
|
||||
end else begin
|
||||
fsm_state <= n_fsm_state;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// Responsible for updating the internal value of the txd_reg.
|
||||
always @(posedge clk) begin : p_txd_reg
|
||||
if(!resetn) begin
|
||||
txd_reg <= 1'b1;
|
||||
end else if(fsm_state == FSM_IDLE) begin
|
||||
txd_reg <= 1'b1;
|
||||
end else if(fsm_state == FSM_START) begin
|
||||
txd_reg <= 1'b0;
|
||||
end else if(fsm_state == FSM_SEND) begin
|
||||
txd_reg <= data_to_send[0];
|
||||
end else if(fsm_state == FSM_STOP) begin
|
||||
txd_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue