added vivado on makefile (make vivado)

.gitignore

@@ -9,6 +9,15 @@ testbench/xsim/*backup*
 testbench/xsim/*.log
 testbench/xsim/*.pb
 testbench/xsim/*.wdb
+example_demo/*/build/*
+example_demo/build_logs*
+*.fasm
+*.frames
+*.bin
+*.json
+*.bba
+*toolchain-nix*
+testbench/ddr3_dimm_micron_sim_behav.wcfg
 
 # But do not ignore testbench/xsim/test_*.log
 !testbench/xsim/test_*.log

example_demo/alinx_ax7103b/Makefile

@@ -29,11 +29,11 @@ JTAG_LINK ?= -c digilent_hs2
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -52,18 +52,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/alinx_ax7103b/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/alinx_ax7325b/Makefile

@@ -4,6 +4,7 @@ PART = xc7k325tffg900-2
 CHIPDB  = ${KINTEX7_CHIPDB}
 ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
 
+
 #############################################################################################
 NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
 NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
@@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
 JTAG_LINK ?= -c digilent_hs2
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -53,18 +53,63 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/alinx_ax7325b/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/arty_s7/Makefile

@@ -5,6 +5,7 @@ PART = xc7s50csga324-1
 CHIPDB  = ${SPARTAN7_CHIPDB}
 ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
 
+
 #############################################################################################
 NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
 NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
@@ -26,16 +27,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
 JTAG_LINK ?= --board ${BOARD}
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -54,18 +54,63 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}_vivado.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/arty_s7/arty_ddr3_vivado.xdc

@@ -0,0 +1,265 @@
+## This file is a general .xdc for the Arty S7-50 Rev. E
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signals
+set_property -dict {PACKAGE_PIN R2 IOSTANDARD SSTL135} [get_ports i_clk]
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk]
+
+## LEDs
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
+set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
+set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
+
+## Buttons
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports i_rst]
+
+## USB-UART Interface
+set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports tx]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports rx]
+
+
+############## DDR3 ##################
+# DQ PINS
+set_property SLEW FAST [get_ports {ddr3_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
+set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
+set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
+set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
+set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[3]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
+set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[4]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
+set_property PACKAGE_PIN M4 [get_ports {ddr3_dq[5]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
+set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[6]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
+set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[7]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
+set_property PACKAGE_PIN N4 [get_ports {ddr3_dq[8]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
+set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[9]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
+set_property PACKAGE_PIN N1 [get_ports {ddr3_dq[10]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
+set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[11]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
+set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[12]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
+set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[13]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
+set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[14]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
+set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[15]}]
+
+# Address Pins
+set_property SLEW FAST [get_ports {ddr3_addr[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
+set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[13]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
+set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[12]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
+set_property PACKAGE_PIN T5 [get_ports {ddr3_addr[11]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
+set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[10]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
+set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
+set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[8]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
+set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[7]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
+set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
+set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
+set_property PACKAGE_PIN T3 [get_ports {ddr3_addr[4]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
+set_property PACKAGE_PIN V4 [get_ports {ddr3_addr[3]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
+set_property PACKAGE_PIN V2 [get_ports {ddr3_addr[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
+set_property PACKAGE_PIN R4 [get_ports {ddr3_addr[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
+set_property PACKAGE_PIN U2 [get_ports {ddr3_addr[0]}]
+
+# Bank Pins
+set_property SLEW FAST [get_ports {ddr3_ba[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
+set_property PACKAGE_PIN U3 [get_ports {ddr3_ba[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_ba[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
+set_property PACKAGE_PIN T1 [get_ports {ddr3_ba[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_ba[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
+set_property PACKAGE_PIN V5 [get_ports {ddr3_ba[0]}]
+
+# Command Pins
+set_property SLEW FAST [get_ports ddr3_ras_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
+set_property PACKAGE_PIN U1 [get_ports ddr3_ras_n]
+
+set_property SLEW FAST [get_ports ddr3_cas_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
+set_property PACKAGE_PIN V3 [get_ports ddr3_cas_n]
+
+set_property SLEW FAST [get_ports ddr3_we_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
+set_property PACKAGE_PIN P7 [get_ports ddr3_we_n]
+
+set_property SLEW FAST [get_ports ddr3_reset_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
+set_property PACKAGE_PIN J6 [get_ports ddr3_reset_n]
+
+set_property SLEW FAST [get_ports ddr3_cke]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
+set_property PACKAGE_PIN T2 [get_ports ddr3_cke]
+
+
+set_property SLEW FAST [get_ports ddr3_odt]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
+set_property PACKAGE_PIN P5 [get_ports ddr3_odt]
+
+
+set_property SLEW FAST [get_ports ddr3_cs_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n]
+set_property PACKAGE_PIN R3 [get_ports ddr3_cs_n]
+
+# Data Mask Pins
+set_property SLEW FAST [get_ports {ddr3_dm[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
+set_property PACKAGE_PIN K4 [get_ports {ddr3_dm[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dm[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
+set_property PACKAGE_PIN M3 [get_ports {ddr3_dm[1]}]
+
+# DQS Pins
+set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
+set_property PACKAGE_PIN K1 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
+set_property PACKAGE_PIN N3 [get_ports {ddr3_dqs_p[1]}]
+set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_n[1]}]
+
+# Clock Pins
+set_property SLEW FAST [get_ports ddr3_clk_p]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]
+
+set_property SLEW FAST [get_ports ddr3_clk_n]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
+set_property PACKAGE_PIN R5 [get_ports ddr3_clk_p]
+set_property PACKAGE_PIN T4 [get_ports ddr3_clk_n]
+
+
+
+
+
+## Configuration options, can be used for all designs
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
+## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
+## and to be able to use this pin as an ordinary I/O the following property must
+## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
+## used the internal reference is set to half that value (i.e. 0.675v). Note that
+## this property must be set even if SW3 is not used in the design.
+ set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+
+

example_demo/arty_s7/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/enclustra_kx2_st1/Makefile

@@ -26,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
 JTAG_LINK ?= -c digilent_hs2
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -54,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/enclustra_kx2_st1/clk_wiz.v

@@ -2,14 +2,14 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  output        clk_out5,
+  output wire        clk_out5,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/nexys_video/Makefile

@@ -4,6 +4,7 @@ PART = xc7a200tsbg484-1
 CHIPDB  = ${ARTIX7_CHIPDB}
 ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
 
+
 #############################################################################################
 NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
 NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
@@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
+JTAG_LINK ?= -c digilent_hs2
-JTAG_LINK ?= --board ${BOARD}
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -53,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/nexys_video/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/nexys_video/nexysvideo_ddr3.v

@@ -216,9 +216,7 @@
             .io_ddr3_dqs_n(ddr3_dqs_n),
             .o_ddr3_dm(ddr3_dm),
             .o_ddr3_odt(ddr3_odt), // on-die termination
-            .o_debug1(o_debug1),
+            .o_debug1(o_debug1)
-            .o_debug2(o_debug2),
-            .o_debug3()
         );
 
 endmodule

example_demo/qmtech_kintex_7/Makefile

@@ -4,6 +4,7 @@ PART = xc7k325tffg676-1
 CHIPDB  = ${KINTEX7_CHIPDB}
 ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
 
+
 #############################################################################################
 NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
 NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
@@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
 JTAG_LINK ?= -c digilent_hs2
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -53,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/qmtech_kintex_7/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/qmtech_wukong/Makefile

@@ -26,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
 JTAG_LINK ?= -c digilent_hs2
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -54,18 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}_vivado.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.bit
+	rm -f *.bit
-	@rm -f *.frames
+	rm -f *.frames
-	@rm -f *.fasm
+	rm -f *.fasm
-	@rm -f *.json
+	rm -f *.json
-	@rm -f *.bin
+	rm -f *.bin
-	@rm -f *.bba
+	rm -f *.bba
-	
+	rm -rf ${BUILDDIR}
-.PHONY: pnrclean
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/qmtech_wukong/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/qmtech_wukong/wukong_ddr3_vivado.xdc

@@ -0,0 +1,537 @@
+## Clock Signals
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports i_clk]
+create_clock -period 20.000 -name sys_clk_pin -waveform {0.000 10.000} -add [get_ports i_clk]
+
+## Reset
+set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports i_rst_n]
+
+## LEDs
+set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
+set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
+
+## DDR3
+# PadFunction: IO_L18N_T2_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[0]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
+
+set_property PACKAGE_PIN D21 [get_ports {ddr3_dq[0]}]
+
+
+
+# PadFunction: IO_L16P_T2_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[1]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
+
+set_property PACKAGE_PIN C21 [get_ports {ddr3_dq[1]}]
+
+
+
+# PadFunction: IO_L17P_T2_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[2]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
+
+set_property PACKAGE_PIN B22 [get_ports {ddr3_dq[2]}]
+
+
+
+# PadFunction: IO_L16N_T2_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[3]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
+
+set_property PACKAGE_PIN B21 [get_ports {ddr3_dq[3]}]
+
+
+
+# PadFunction: IO_L13P_T2_MRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[4]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
+
+set_property PACKAGE_PIN D19 [get_ports {ddr3_dq[4]}]
+
+
+
+# PadFunction: IO_L14P_T2_SRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[5]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
+
+set_property PACKAGE_PIN E20 [get_ports {ddr3_dq[5]}]
+
+
+
+# PadFunction: IO_L13N_T2_MRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[6]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
+
+set_property PACKAGE_PIN C19 [get_ports {ddr3_dq[6]}]
+
+
+
+# PadFunction: IO_L14N_T2_SRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[7]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
+
+set_property PACKAGE_PIN D20 [get_ports {ddr3_dq[7]}]
+
+
+
+# PadFunction: IO_L19N_T3_VREF_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[8]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
+
+set_property PACKAGE_PIN C23 [get_ports {ddr3_dq[8]}]
+
+
+
+# PadFunction: IO_L24P_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[9]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
+
+set_property PACKAGE_PIN D23 [get_ports {ddr3_dq[9]}]
+
+
+
+# PadFunction: IO_L23N_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[10]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
+
+set_property PACKAGE_PIN B24 [get_ports {ddr3_dq[10]}]
+
+
+
+# PadFunction: IO_L20P_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[11]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
+
+set_property PACKAGE_PIN B25 [get_ports {ddr3_dq[11]}]
+
+
+
+# PadFunction: IO_L23P_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[12]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
+
+set_property PACKAGE_PIN C24 [get_ports {ddr3_dq[12]}]
+
+
+
+# PadFunction: IO_L22P_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[13]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
+
+set_property PACKAGE_PIN C26 [get_ports {ddr3_dq[13]}]
+
+
+
+# PadFunction: IO_L20N_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[14]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
+
+set_property PACKAGE_PIN A25 [get_ports {ddr3_dq[14]}]
+
+
+
+# PadFunction: IO_L22N_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dq[15]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
+
+set_property PACKAGE_PIN B26 [get_ports {ddr3_dq[15]}]
+
+
+
+# PadFunction: IO_L4P_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[13]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
+
+set_property PACKAGE_PIN G15 [get_ports {ddr3_addr[13]}]
+
+
+
+# PadFunction: IO_L12N_T1_MRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[12]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
+
+set_property PACKAGE_PIN C18 [get_ports {ddr3_addr[12]}]
+
+
+
+# PadFunction: IO_L1N_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[11]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
+
+set_property PACKAGE_PIN H15 [get_ports {ddr3_addr[11]}]
+
+
+
+# PadFunction: IO_L5N_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[10]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
+
+set_property PACKAGE_PIN F20 [get_ports {ddr3_addr[10]}]
+
+
+
+# PadFunction: IO_L4N_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[9]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
+
+set_property PACKAGE_PIN F15 [get_ports {ddr3_addr[9]}]
+
+
+
+# PadFunction: IO_L1P_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[8]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
+
+set_property PACKAGE_PIN H14 [get_ports {ddr3_addr[8]}]
+
+
+
+# PadFunction: IO_L8P_T1_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[7]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
+
+set_property PACKAGE_PIN E16 [get_ports {ddr3_addr[7]}]
+
+
+
+# PadFunction: IO_L6P_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[6]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
+
+set_property PACKAGE_PIN H16 [get_ports {ddr3_addr[6]}]
+
+
+
+# PadFunction: IO_L8N_T1_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[5]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
+
+set_property PACKAGE_PIN D16 [get_ports {ddr3_addr[5]}]
+
+
+
+# PadFunction: IO_L6N_T0_VREF_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[4]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
+
+set_property PACKAGE_PIN G16 [get_ports {ddr3_addr[4]}]
+
+
+
+# PadFunction: IO_L7P_T1_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[3]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
+
+set_property PACKAGE_PIN C17 [get_ports {ddr3_addr[3]}]
+
+
+
+# PadFunction: IO_L2N_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[2]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
+
+set_property PACKAGE_PIN F17 [get_ports {ddr3_addr[2]}]
+
+
+
+# PadFunction: IO_L2P_T0_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[1]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
+
+set_property PACKAGE_PIN G17 [get_ports {ddr3_addr[1]}]
+
+
+
+# PadFunction: IO_L11P_T1_SRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_addr[0]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
+
+set_property PACKAGE_PIN E17 [get_ports {ddr3_addr[0]}]
+
+
+
+# PadFunction: IO_L9P_T1_DQS_16
+
+set_property SLEW FAST [get_ports {ddr3_ba[2]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
+
+set_property PACKAGE_PIN A17 [get_ports {ddr3_ba[2]}]
+
+
+
+# PadFunction: IO_L12P_T1_MRCC_16
+
+set_property SLEW FAST [get_ports {ddr3_ba[1]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
+
+set_property PACKAGE_PIN D18 [get_ports {ddr3_ba[1]}]
+
+
+
+# PadFunction: IO_L7N_T1_16
+
+set_property SLEW FAST [get_ports {ddr3_ba[0]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
+
+set_property PACKAGE_PIN B17 [get_ports {ddr3_ba[0]}]
+
+
+
+# PadFunction: IO_L10N_T1_16
+
+set_property SLEW FAST [get_ports ddr3_ras_n]
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
+
+set_property PACKAGE_PIN A19 [get_ports ddr3_ras_n]
+
+
+
+# PadFunction: IO_L10P_T1_16
+
+set_property SLEW FAST [get_ports ddr3_cas_n]
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
+
+set_property PACKAGE_PIN B19 [get_ports ddr3_cas_n]
+
+
+
+# PadFunction: IO_L9N_T1_DQS_16
+
+set_property SLEW FAST [get_ports ddr3_we_n]
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
+
+set_property PACKAGE_PIN A18 [get_ports ddr3_we_n]
+
+
+
+# PadFunction: IO_0_16
+
+set_property SLEW FAST [get_ports ddr3_reset_n]
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
+
+set_property PACKAGE_PIN H17 [get_ports ddr3_reset_n]
+
+
+
+# PadFunction: IO_L11N_T1_SRCC_16
+
+set_property SLEW FAST [get_ports ddr3_cke]
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
+
+set_property PACKAGE_PIN E18 [get_ports ddr3_cke]
+
+
+
+# PadFunction: IO_L5P_T0_16
+
+set_property SLEW FAST [get_ports ddr3_odt]
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
+
+set_property PACKAGE_PIN G19 [get_ports ddr3_odt]
+
+
+
+# PadFunction: IO_L17N_T2_16
+
+set_property SLEW FAST [get_ports {ddr3_dm[0]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
+
+set_property PACKAGE_PIN A22 [get_ports {ddr3_dm[0]}]
+
+
+
+# PadFunction: IO_L19P_T3_16
+
+set_property SLEW FAST [get_ports {ddr3_dm[1]}]
+
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
+
+set_property PACKAGE_PIN C22 [get_ports {ddr3_dm[1]}]
+
+
+
+# PadFunction: IO_L15P_T2_DQS_16
+
+set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
+
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
+
+
+
+
+# PadFunction: IO_L15N_T2_DQS_16
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
+
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
+
+set_property PACKAGE_PIN B20 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN A20 [get_ports {ddr3_dqs_n[0]}]
+
+
+
+# PadFunction: IO_L21P_T3_DQS_16
+
+set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
+
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
+
+
+
+
+# PadFunction: IO_L21N_T3_DQS_16
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
+
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
+
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
+
+set_property PACKAGE_PIN A23 [get_ports {ddr3_dqs_p[1]}]
+set_property PACKAGE_PIN A24 [get_ports {ddr3_dqs_n[1]}]
+
+
+
+# PadFunction: IO_L3P_T0_DQS_16
+
+set_property SLEW FAST [get_ports ddr3_clk_p]
+
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]
+
+
+
+
+# PadFunction: IO_L3N_T0_DQS_16
+
+set_property SLEW FAST [get_ports ddr3_clk_n]
+
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
+
+set_property PACKAGE_PIN F18 [get_ports ddr3_clk_p]
+set_property PACKAGE_PIN F19 [get_ports ddr3_clk_n]
+
+
+
+## UART
+set_property PACKAGE_PIN F3 [get_ports rx]
+set_property IOSTANDARD LVCMOS33 [get_ports rx]
+set_property PACKAGE_PIN E3 [get_ports tx]
+set_property IOSTANDARD LVCMOS33 [get_ports tx]
+
+
+set_property INTERNAL_VREF 0.675 [get_iobanks 16]
+# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+
+
+# ## Place the IOSERDES_train manually (else the tool will place this blocks which can block the route for CLKB0 (OBUFDS for ddr3_clk_p))
+# set_property LOC OLOGIC_X0Y91 [get_cells {ddr3_top/ddr3_phy_inst/genblk5[1].OSERDESE2_train}]
+# set_property LOC ILOGIC_X0Y94 [get_cells {ddr3_top/ddr3_phy_inst/genblk5[0].ISERDESE2_train}]
+

example_demo/run_make_all.sh

@@ -1,6 +1,7 @@
 #!/bin/bash
 
 # Create a logs directory to store all log files
+rm -rf build_logs
 mkdir -p build_logs
 
 # Loop through each item in the current directory
@@ -14,6 +15,15 @@ for dir in */; do
             cd "$dir"
             make clean
             make
+            echo ""
+            echo "DONE OPENXC7"
+            echo ""
+            echo ""
+            make vivado
+            echo ""
+            echo "DONE VIVADO"
+            echo ""
+            echo ""
             cd ..
             echo "===== Finished $dir ====="
         } &> "$log_file"

example_demo/sechzig_mx2/Makefile

@@ -4,6 +4,7 @@ PART = xc7a35tftg256-2
 CHIPDB  = ${ARTIX7_CHIPDB}
 ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
 
+
 #############################################################################################
 NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
 NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
@@ -25,16 +26,15 @@ TOP_VERILOG ?= ${TOP}.v
 
 PNR_DEBUG ?= # --verbose --debug
 
-BOARD ?= UNKNOWN
+JTAG_LINK ?= -c digilent_hs2
-JTAG_LINK ?= --board ${BOARD}
 
 XDC ?= ${PROJECT}.xdc
 
-.PHONY: all
+.PHONY: openxc7
-all: ${PROJECT}.bit
+openxc7: ${PROJECT}_openxc7.bit
 
 .PHONY: program
-program: ${PROJECT}.bit
+program: ${PROJECT}_openxc7.bit
 	openFPGALoader ${JTAG_LINK} --bitstream $<
 
 ${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
@@ -53,17 +53,62 @@ ${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
 ${PROJECT}.frames: ${PROJECT}.fasm
 	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
 
-${PROJECT}.bit: ${PROJECT}.frames
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
 	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
 
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
 .PHONY: clean
 clean:
-	@rm -f *.frames
+	rm -f *.bit
-	@rm -f *.fasm
+	rm -f *.frames
-	@rm -f *.json
+	rm -f *.fasm
-	@rm -f *.bin
+	rm -f *.json
-	@rm -f *.bba
+	rm -f *.bin
-	
+	rm -f *.bba
-.PHONY: pnrclean
+	rm -rf ${BUILDDIR}
-pnrclean:
-	rm *.fasm *.frames *.bit 

example_demo/sechzig_mx2/clk_wiz.v

@@ -2,13 +2,13 @@
 
 module clk_wiz
  (
-  input         clk_in1,
+  input wire         clk_in1,
-  output        clk_out1,
+  output wire        clk_out1,
-  output        clk_out2,
+  output wire        clk_out2,
-  output        clk_out3,
+  output wire        clk_out3,
-  output        clk_out4,
+  output wire        clk_out4,
-  input         reset,
+  input wire         reset,
-  output        locked
+  output wire        locked
  );
   wire        clk_out1_clk_wiz_0;
   wire        clk_out2_clk_wiz_0;

example_demo/sechzig_mx2/sechzig_mx2_ddr3.v

@@ -207,9 +207,7 @@
             .io_ddr3_dqs_n(ddr3_dqs_n),
             .o_ddr3_dm(ddr3_dm),
             .o_ddr3_odt(ddr3_odt), // on-die termination
-            .o_debug1(o_debug1),
+            .o_debug1(o_debug1)
-            .o_debug2(),
-            .o_debug3()
         );
 
 endmodule