diff --git a/kintex_switch_files/ddr3.txt b/kintex_switch_files/ddr3.txt
index c1f067b..327088a 100644
--- a/kintex_switch_files/ddr3.txt
+++ b/kintex_switch_files/ddr3.txt
@@ -33,7 +33,6 @@
 ################################################################################
 ##
 ## }}}
-
 # Wishbone 1
 @PREFIX=ddr3_controller
 @DEVID=DDR3_CONTROLLER
@@ -76,8 +75,8 @@
                     @$(DEVID)COL_BITS = 10,  // width of column address
                     @$(DEVID)BA_BITS  =  3,  // width of bank address
                     @$(DEVID)DQ_BITS  =  8,  // Size of one octet
-                    @$(DEVID)LANES = @$(NLANES), //8 lanes of DQ
-                    @$(DEVID)AUX_WIDTH = 1,
+                    @$(DEVID)LANES = 8, //@$(NLANES), //8 lanes of DQ
+                    @$(DEVID)AUX_WIDTH = 8, //must be 8 bits or more (also used in internal test and calibration)
                     @$(DEVID)SERDES_RATIO = $rtoi(@$(DEVID)CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
                     //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
                     @$(DEVID)CMD_LEN = 4 + 3 + @$(DEVID)BA_BITS + @$(DEVID)ROW_BITS;
@@ -112,13 +111,17 @@
 	wire    [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] @$(PREFIX)_cmd;
 	wire    @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control;
 	wire    @$(PREFIX)_toggle_dqs;
-	wire    [@$(SLAVE.BUS.WIDTH)-1:0] @$(PREFIX)_data;
-	wire    [@$(SLAVE.BUS.WIDTH)/8-1:0] @$(PREFIX)_dm;
+	wire    [@$(DEVID)DQ_BITS*@$(DEVID)LANES*8-1:0] @$(PREFIX)_data;
+	wire    [(@$(DEVID)DQ_BITS*@$(DEVID)LANES*8)/8-1:0] @$(PREFIX)_dm;
 	wire    [4:0] @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein;
 	wire    [4:0] @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein;
 	wire    [@$(DEVID)LANES-1:0] @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld;
 	wire    [@$(DEVID)LANES-1:0] @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld;
 	wire    [@$(DEVID)LANES-1:0] @$(PREFIX)_bitslip;
+	wire    @$(PREFIX)_write_leveling_calib;
+	wire    @$(PREFIX)_reset;
+	wire    [@$(DEVID)LANES-1:0] @$(PREFIX)_debug_read_dqs_p, @$(PREFIX)_debug_read_dqs_n;
+	wire    @$(PREFIX)_debug_clk_p, @$(PREFIX)_debug_clk_n;
 	// }}}
 @TOP.MAIN=
         	// DDR3 Controller-PHY Interface
@@ -132,8 +135,27 @@
         	@$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein,
         	@$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld,
         	@$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld,
-        	@$(PREFIX)_bitslip
+        	@$(PREFIX)_bitslip,
+        	@$(PREFIX)_write_leveling_calib,
+        	@$(PREFIX)_reset
 @TOP.INSERT=
+/*
+    wire clk_locked;
+    wire controller_clk, ddr3_clk, ref_ddr3_clk, ddr3_clk_90;
+    clk_wiz_0 clk_ddr3
+     (
+      // Clock out ports
+      .clk_out1(controller_clk),
+      .clk_out2(ddr3_clk),
+      .clk_out3(ref_ddr3_clk),
+      .clk_out4(ddr3_clk_90),
+      // Status and control signals
+      .reset(s_reset),
+      .locked(clk_locked),
+     // Clock in ports
+      .clk_in1(s_clk200)
+     );
+*/
 	// DDR3 PHY Instantiation
 	ddr3_phy #(
 		.ROW_BITS(@$(DEVID)ROW_BITS), //width of row address
@@ -141,14 +163,17 @@
 		.DQ_BITS(@$(DEVID)DQ_BITS),  //width of DQ
 		.LANES(@$(DEVID)LANES), //8 lanes of DQ
 		.CONTROLLER_CLK_PERIOD(@$(DEVID)CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
-		.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device 
+		.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device 
+		.ODELAY_SUPPORTED(1)
 	) ddr3_phy_inst (
             // clock and reset
             .i_controller_clk(s_clk), 
             .i_ddr3_clk(s_clk4x),
             .i_ref_clk(s_clk200),
+            .i_ddr3_clk_90(0), //required only when ODELAY_SUPPORTED is zero
             .i_rst_n(!s_reset),
             // Controller Interface
+            .i_controller_reset(@$(PREFIX)_reset),
             .i_controller_cmd(@$(PREFIX)_cmd),
             .i_controller_dqs_tri_control(@$(PREFIX)_dqs_tri_control), 
             .i_controller_dq_tri_control(@$(PREFIX)_dq_tri_control),
@@ -164,6 +189,7 @@
             .i_controller_idelay_data_ld(@$(PREFIX)_idelay_data_ld), 
             .i_controller_idelay_dqs_ld(@$(PREFIX)_idelay_dqs_ld),
             .i_controller_bitslip(@$(PREFIX)_bitslip),
+            .i_controller_write_leveling_calib(@$(PREFIX)_write_leveling_calib),
             .o_controller_iserdes_data(@$(PREFIX)_iserdes_data),
             .o_controller_iserdes_dqs(@$(PREFIX)_iserdes_dqs),
             .o_controller_iserdes_bitslip_reference(@$(PREFIX)_iserdes_bitslip_reference),
@@ -183,9 +209,12 @@
             .io_ddr3_dqs(io_ddr3_dqs_p),
             .io_ddr3_dqs_n(io_ddr3_dqs_n),
             .o_ddr3_dm(o_ddr3_dm),
-            .o_ddr3_odt(o_ddr3_odt[0]) // on-die termination
+            .o_ddr3_odt(o_ddr3_odt[0]), // on-die termination
+            // DEBUG PHY
+            .o_ddr3_debug_read_dqs_p(@$(PREFIX)_debug_read_dqs_p),
+            .o_ddr3_debug_read_dqs_n(@$(PREFIX)_debug_read_dqs_n)
         );
-
+        //assign	o_tp = {@$(PREFIX)_debug_read_dqs_n[1:0],@$(PREFIX)_debug_read_dqs_p[1:0]};
         assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank
         assign o_ddr3_cke[1] = 0; // set to 0 (disabled) since controller only supports single rank
         assign o_ddr3_odt[1] = 0; // set to 0 (disabled) since controller only supports single rank
@@ -195,7 +224,17 @@
 	begin : GEN_UNUSED_@$(DEVID)_ASSIGN
 		assign o_ddr3_a[@$(PREFIX)gen_index] = 0;
 	end endgenerate
- 	
+	/*
+	// OBUFDS: Differential Output Buffer
+    // 7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    OBUFDS OBUFDS_inst (
+    .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+    .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+    .I(s_clk4x) // Buffer input
+    );
+    // End of OBUFDS_inst instantiation
+ 	*/
 @MAIN.PORTLIST=
 		// DDR3 Controller Interface
 		i_@$(PREFIX)_iserdes_data, i_@$(PREFIX)_iserdes_dqs,
@@ -208,7 +247,9 @@
 		o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein,
 		o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld,
 		o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld,
-		o_@$(PREFIX)_bitslip
+		o_@$(PREFIX)_bitslip,
+		o_@$(PREFIX)_leveling_calib,
+		o_@$(PREFIX)_reset
 @MAIN.PARAM=@$(TOP.PARAM)
 @MAIN.IODECL=
 	// DDR3 Controller I/O declarations
@@ -220,18 +261,20 @@
 	output wire    [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] o_@$(PREFIX)_cmd;
 	output wire    o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control;
 	output wire    o_@$(PREFIX)_toggle_dqs;
-	output wire    [@$(SLAVE.BUS.WIDTH)-1:0] o_@$(PREFIX)_data;
-	output wire    [@$(SLAVE.BUS.WIDTH)/8-1:0] o_@$(PREFIX)_dm;
+	output wire    [@$(DEVID)DQ_BITS*@$(DEVID)LANES*8-1:0] o_@$(PREFIX)_data;
+	output wire    [(@$(DEVID)DQ_BITS*@$(DEVID)LANES*8)/8-1:0] o_@$(PREFIX)_dm;
 	output wire    [4:0] o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein;
 	output wire    [4:0] o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein;
 	output wire    [@$(DEVID)LANES-1:0] o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld;
 	output wire    [@$(DEVID)LANES-1:0] o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld;
 	output wire    [@$(DEVID)LANES-1:0] o_@$(PREFIX)_bitslip;
+	output wire    o_@$(PREFIX)_leveling_calib;
+	output wire    o_@$(PREFIX)_reset;
 	// }}}
 @MAIN.DEFNS=
 	// Verilator lint_off UNUSED
 	wire	[@$(DEVID)AUX_WIDTH-1:0]	@$(PREFIX)_aux_out;
-	wire	[31:0]	@$(PREFIX)_debug1, @$(PREFIX)_debug2;
+	wire	[31:0]	@$(PREFIX)_debug1, @$(PREFIX)_debug2, @$(PREFIX)_debug3;
 	// Verilator lint_on  UNUSED
 @MAIN.INSERT=
 	////////////////////////////////////////////////////////////////////////
@@ -247,6 +290,8 @@
             .DQ_BITS(@$(DEVID)DQ_BITS),  //width of DQ
             .LANES(@$(DEVID)LANES), //8 lanes of DQ
             .AUX_WIDTH(@$(DEVID)AUX_WIDTH), //
+            .MICRON_SIM(0), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+            .ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
             .OPT_LOWPOWER(1), //1 = low power, 0 = low logic
             .OPT_BUS_ABORT(1)  //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
 	) ddr3_controller_inst (
@@ -279,9 +324,12 @@
             .o_phy_idelay_data_ld(o_@$(PREFIX)_idelay_data_ld), 
             .o_phy_idelay_dqs_ld(o_@$(PREFIX)_idelay_dqs_ld),
             .o_phy_bitslip(o_@$(PREFIX)_bitslip),
+            .o_phy_write_leveling_calib(o_@$(PREFIX)_leveling_calib),
+            .o_phy_reset(o_@$(PREFIX)_reset),
             // Debug port
             .o_debug1(@$(PREFIX)_debug1),
-            .o_debug2(@$(PREFIX)_debug2)
+            .o_debug2(@$(PREFIX)_debug2),
+            .o_debug3(@$(PREFIX)_debug3)
         );
 	// }}}
 ##
diff --git a/kintex_switch_files/ddr3scope.txt b/kintex_switch_files/ddr3scope.txt
index 6c43190..ec0ca1c 100644
--- a/kintex_switch_files/ddr3scope.txt
+++ b/kintex_switch_files/ddr3scope.txt
@@ -54,3 +54,15 @@
 @INT.DDR3SCOPE2.PIC=altpic
 @INT.DDR3SCOPE2.WIRE=@$(PREFIX)_int
 @MAIN.DEFNS=
+#
+#
+@PREFIX=scope3_ddr3
+@DEVID=DDR3SCOPE3
+@TARGET=ddr3_controller
+@TRIGGER=ddr3_controller_debug3[31]
+@DEBUG=@$(TARGET)_debug3[30:0]
+@$LOG_CAPTURE_SIZE=10
+@INCLUDEFILE=wbscopc.txt
+@INT.DDR3SCOPE2.PIC=altpic
+@INT.DDR3SCOPE2.WIRE=@$(PREFIX)_int
+@MAIN.DEFNS=
diff --git a/kintex_switch_files/ddr3scope1.cpp b/kintex_switch_files/ddr3scope1.cpp
index 75a5109..a5fd874 100644
--- a/kintex_switch_files/ddr3scope1.cpp
+++ b/kintex_switch_files/ddr3scope1.cpp
@@ -78,17 +78,40 @@ public:
 
 	virtual	void	define_traces(void) {
         /*
-      assign o_debug1 = {debug_trigger, o_wb2_stall, lane[2:0], dqs_start_index_stored[2:0], dqs_target_index[2:0], delay_before_read_data[2:0], 
-                o_phy_idelay_dqs_ld[lane], state_calibrate[4:0], dqs_store[11:0]};
-        */
-        register_trace("o_wb2_stall",1,30);     
-		register_trace("lane",3,27);
-		register_trace("dqs_start_index_stored",3,24);
-		register_trace("dqs_target_index",3,21);
-		register_trace("delay_before_read_data",3,18);
-		register_trace("o_phy_idelay_dqs_ld",1,17);
-		register_trace("state_calibrate",5,12);
-		register_trace("dqs_store",12,0);
+       assign o_debug1 = {debug_trigger, 2'b00, delay_before_read_data[3:0] ,i_phy_idelayctrl_rdy, lane[2:0], dqs_start_index_stored[4:0], 
+        dqs_target_index[4:0], instruction_address[4:0], state_calibrate[4:0], o_wb2_stall};    
+        
+        register_trace("delay_before_read_data",4,25);     
+		register_trace("i_phy_idelayctrl_rdy",1,24);
+		register_trace("lane",3,21);
+		register_trace("dqs_start_index_stored",5,16);
+		register_trace("dqs_target_index",5,11);
+		register_trace("instruction_address",5,6);
+		register_trace("state_calibrate",5,1);
+		register_trace("o_wb2_stall",1,0);
+		*/
+		/*
+		 assign o_debug1 = {debug_trigger,stage1_we,stage1_col[5:0],stage1_data[7:0],stage1_dm[15:0]};
+		
+		register_trace("stage1_we",1,30);
+		register_trace("stage1_col",6,24);
+		register_trace("stage1_data",8,16);
+		register_trace("stage1_dm",16,0);
+		*/
+		/*
+		    assign o_debug1 = {debug_trigger,i_phy_iserdes_dqs[7:0],state_calibrate[4:0], instruction_address[4:0],o_phy_idelay_dqs_ld,o_phy_idelay_data_ld,o_phy_odelay_data_ld,o_phy_odelay_dqs_ld,
+             delay_before_read_data[2:0],delay_before_write_level_feedback[4:0],lane};
+                 assign o_debug1 = {debug_trigger,i_phy_iserdes_dqs[7:0],state_calibrate[4:0], instruction_address[4:0],reset_from_wb2,
+                        repeat_test, delay_before_read_data[2:0], delay_before_write_level_feedback[4:0],lane[2:0]};
+         */ 
+        register_trace("i_phy_iserdes_dqs",8,23);
+        register_trace("state_calibrate",5,18);
+        register_trace("instruction_address",5,13);
+        register_trace("reset_from_wb2",1,12);
+        register_trace("repeat_test",1,11);
+        register_trace("delay_before_read_data",3,8);
+        register_trace("delay_before_write_level_feedback",5,3);
+        register_trace("lane",3,0);
 	}
 };
 
diff --git a/kintex_switch_files/ddr3scope2.cpp b/kintex_switch_files/ddr3scope2.cpp
index 4b23e0e..d7ddb43 100644
--- a/kintex_switch_files/ddr3scope2.cpp
+++ b/kintex_switch_files/ddr3scope2.cpp
@@ -80,9 +80,9 @@ public:
         /*
         assign o_debug2 = {debug_trigger, idelay_dqs_cntvaluein[lane][4:0], idelay_data_cntvaluein[lane][4:0], i_phy_iserdes_dqs[15:0], 
                 o_phy_dqs_tri_control, o_phy_dq_tri_control,
-                (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b0}}), (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b1}}), (i_phy_iserdes_data < { {(DQ_BITS*LANES*4){1'b0}}, {(DQ_BITS*LANES*4){1'b1}} } )
+                (i_phy_iserdes_data == 0), (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b1}}), (i_phy_iserdes_data < { {(DQ_BITS*LANES*4){1'b0}}, {(DQ_BITS*LANES*4){1'b1}} } )
                 }; 
-        */
+        
 
 		register_trace("idelay_dqs_cntvaluein",5,26);
 		register_trace("idelay_data_cntvaluein",5,21);
@@ -93,6 +93,11 @@ public:
 		register_trace("i_phy_iserdes_data_is_zero",1,2);
 		register_trace("i_phy_iserdes_data_all_1s",1,1);
 		register_trace("i_phy_iserdes_data_less_than_half",1,0);
+		*/
+		/*
+		assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
+		*/
+		register_trace("i_phy_iserdes_data_62_32",31,0);
 	}
 };
 
diff --git a/kintex_switch_files/kluster.xdc b/kintex_switch_files/kluster.xdc
index c6c2644..57334ab 100644
--- a/kintex_switch_files/kluster.xdc
+++ b/kintex_switch_files/kluster.xdc
@@ -270,121 +270,121 @@ create_clock -period 5.0 -name SYSCLK -waveform { 0.0 2.50 } -add [get_ports i_c
 
 ### Byte lane #0
 ### {{{
-#set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[0]]
-#set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[1]]
-#set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[2]]
-#set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[3]]
-#set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[4]]
-#set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[5]]
-#set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[6]]
-#set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[7]]
-#set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[0]]
-#set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[0]]
+#set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[0]]
+#set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[1]]
+#set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[2]]
+#set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[3]]
+#set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[4]]
+#set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[5]]
+#set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[6]]
+#set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[7]]
+#set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[0]]
+#set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[0]]
 #set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[0]]
 ### }}}
 
 ### Byte lane #1
 ### {{{
-#set_property -dict {PACKAGE_PIN V16  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[8]]
-#set_property -dict {PACKAGE_PIN V18  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[9]]
-#set_property -dict {PACKAGE_PIN AB20  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[10]]
-#set_property -dict {PACKAGE_PIN AB19  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[11]]
-#set_property -dict {PACKAGE_PIN W15  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[12]]
-#set_property -dict {PACKAGE_PIN V19  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[13]]
-#set_property -dict {PACKAGE_PIN W16  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[14]]
-#set_property -dict {PACKAGE_PIN Y17  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[15]]
-#set_property -dict {PACKAGE_PIN W18  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[1]]
-#set_property -dict {PACKAGE_PIN W19  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[1]]
+#set_property -dict {PACKAGE_PIN V16  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[8]]
+#set_property -dict {PACKAGE_PIN V18  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[9]]
+#set_property -dict {PACKAGE_PIN AB20  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[10]]
+#set_property -dict {PACKAGE_PIN AB19  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[11]]
+#set_property -dict {PACKAGE_PIN W15  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[12]]
+#set_property -dict {PACKAGE_PIN V19  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[13]]
+#set_property -dict {PACKAGE_PIN W16  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[14]]
+#set_property -dict {PACKAGE_PIN Y17  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[15]]
+#set_property -dict {PACKAGE_PIN W18  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[1]]
+#set_property -dict {PACKAGE_PIN W19  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[1]]
 #set_property -dict {PACKAGE_PIN V17  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[1]]
 ### }}}
 
 ### Byte lane #2
 ### {{{
-#set_property -dict {PACKAGE_PIN AF19  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[16]]
-#set_property -dict {PACKAGE_PIN AE17  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[17]]
-#set_property -dict {PACKAGE_PIN AE15  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[18]]
-#set_property -dict {PACKAGE_PIN AF15  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[19]]
-#set_property -dict {PACKAGE_PIN AF20  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[20]]
-#set_property -dict {PACKAGE_PIN AD16  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[21]]
-#set_property -dict {PACKAGE_PIN AD15  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[22]]
-#set_property -dict {PACKAGE_PIN AF14  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[23]]
-#set_property -dict {PACKAGE_PIN AE18  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[2]]
-#set_property -dict {PACKAGE_PIN AF18  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[2]]
+#set_property -dict {PACKAGE_PIN AF19  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[16]]
+#set_property -dict {PACKAGE_PIN AE17  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[17]]
+#set_property -dict {PACKAGE_PIN AE15  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[18]]
+#set_property -dict {PACKAGE_PIN AF15  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[19]]
+#set_property -dict {PACKAGE_PIN AF20  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[20]]
+#set_property -dict {PACKAGE_PIN AD16  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[21]]
+#set_property -dict {PACKAGE_PIN AD15  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[22]]
+#set_property -dict {PACKAGE_PIN AF14  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[23]]
+#set_property -dict {PACKAGE_PIN AE18  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[2]]
+#set_property -dict {PACKAGE_PIN AF18  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[2]]
 #set_property -dict {PACKAGE_PIN AF17  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[2]]
 ### }}}
 
 ### Byte lane #3
 ### {{{
-#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[24]]
-#set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[25]]
-#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[26]]
-#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[27]]
-#set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[28]]
-#set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[29]]
-#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[30]]
-#set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[31]]
-#set_property -dict {PACKAGE_PIN Y15  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[3]]
-#set_property -dict {PACKAGE_PIN Y16  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[3]]
+#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[24]]
+#set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[25]]
+#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[26]]
+#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[27]]
+#set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[28]]
+#set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[29]]
+#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[30]]
+#set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[31]]
+#set_property -dict {PACKAGE_PIN Y15  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[3]]
+#set_property -dict {PACKAGE_PIN Y16  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[3]]
 #set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[3]]
 ### }}}
 
 ### Byte lane #4
 ### {{{
-#set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[32]]
-#set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[33]]
-#set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[34]]
-#set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[35]]
-#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[36]]
-#set_property -dict {PACKAGE_PIN Y6  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[37]]
-#set_property -dict {PACKAGE_PIN Y5  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[38]]
-#set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[39]]
-#set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[4]]
-#set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[4]]
+#set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[32]]
+#set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[33]]
+#set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[34]]
+#set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[35]]
+#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[36]]
+#set_property -dict {PACKAGE_PIN Y6  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[37]]
+#set_property -dict {PACKAGE_PIN Y5  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[38]]
+#set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[39]]
+#set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[4]]
+#set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[4]]
 #set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[4]]
 ### }}}
 
 ### Byte lane #5
 ### {{{
-#set_property -dict {PACKAGE_PIN AF3  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[40]]
-#set_property -dict {PACKAGE_PIN AE3  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[41]]
-#set_property -dict {PACKAGE_PIN AE2  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[42]]
-#set_property -dict {PACKAGE_PIN AE1  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[43]]
-#set_property -dict {PACKAGE_PIN AE6  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[44]]
-#set_property -dict {PACKAGE_PIN AE5  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[45]]
-#set_property -dict {PACKAGE_PIN AD4  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[46]]
-#set_property -dict {PACKAGE_PIN AD1  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[47]]
-#set_property -dict {PACKAGE_PIN AF5  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[5]]
-#set_property -dict {PACKAGE_PIN AF4  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[5]]
+#set_property -dict {PACKAGE_PIN AF3  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[40]]
+#set_property -dict {PACKAGE_PIN AE3  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[41]]
+#set_property -dict {PACKAGE_PIN AE2  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[42]]
+#set_property -dict {PACKAGE_PIN AE1  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[43]]
+#set_property -dict {PACKAGE_PIN AE6  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[44]]
+#set_property -dict {PACKAGE_PIN AE5  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[45]]
+#set_property -dict {PACKAGE_PIN AD4  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[46]]
+#set_property -dict {PACKAGE_PIN AD1  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[47]]
+#set_property -dict {PACKAGE_PIN AF5  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[5]]
+#set_property -dict {PACKAGE_PIN AF4  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[5]]
 #set_property -dict {PACKAGE_PIN AF2  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[5]]
 ### }}}
 
 ### Byte lane #6
 ### {{{
-#set_property -dict {PACKAGE_PIN W3  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[48]]
-#set_property -dict {PACKAGE_PIN V4  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[49]]
-#set_property -dict {PACKAGE_PIN U2  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[50]]
-#set_property -dict {PACKAGE_PIN U5  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[51]]
-#set_property -dict {PACKAGE_PIN V6  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[52]]
-#set_property -dict {PACKAGE_PIN V3  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[53]]
-#set_property -dict {PACKAGE_PIN U1  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[54]]
-#set_property -dict {PACKAGE_PIN U6  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[55]]
-#set_property -dict {PACKAGE_PIN W6  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[6]]
-#set_property -dict {PACKAGE_PIN W5  IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[6]]
+#set_property -dict {PACKAGE_PIN W3  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[48]]
+#set_property -dict {PACKAGE_PIN V4  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[49]]
+#set_property -dict {PACKAGE_PIN U2  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[50]]
+#set_property -dict {PACKAGE_PIN U5  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[51]]
+#set_property -dict {PACKAGE_PIN V6  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[52]]
+#set_property -dict {PACKAGE_PIN V3  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[53]]
+#set_property -dict {PACKAGE_PIN U1  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[54]]
+#set_property -dict {PACKAGE_PIN U6  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[55]]
+#set_property -dict {PACKAGE_PIN W6  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[6]]
+#set_property -dict {PACKAGE_PIN W5  IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[6]]
 #set_property -dict {PACKAGE_PIN U7  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[6]]
 ### }}}
 
 ### Byte lane #7
 ### {{{
-#set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[56]]
-#set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[57]]
-#set_property -dict {PACKAGE_PIN W1  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[58]]
-#set_property -dict {PACKAGE_PIN V2  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[59]]
-#set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[60]]
-#set_property -dict {PACKAGE_PIN Y3  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[61]]
-#set_property -dict {PACKAGE_PIN Y2  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[62]]
-#set_property -dict {PACKAGE_PIN V1  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[63]]
-#set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[7]]
-#set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[7]]
+#set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[56]]
+#set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[57]]
+#set_property -dict {PACKAGE_PIN W1  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[58]]
+#set_property -dict {PACKAGE_PIN V2  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[59]]
+#set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[60]]
+#set_property -dict {PACKAGE_PIN Y3  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[61]]
+#set_property -dict {PACKAGE_PIN Y2  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[62]]
+#set_property -dict {PACKAGE_PIN V1  IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[63]]
+#set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[7]]
+#set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[7]]
 #set_property -dict {PACKAGE_PIN Y1  IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[7]]
 ### }}}
 
@@ -453,8 +453,8 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 set_property INTERNAL_VREF 0.750 [get_iobanks 32]
 set_property INTERNAL_VREF 0.750 [get_iobanks 33]
 set_property INTERNAL_VREF 0.750 [get_iobanks 34]
-#set_property DCI_CASCADE {{32}} [get_iobanks 34]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
+set_property BITSTREAM.STARTUP.MATCH_CYCLE 6 [current_design]