luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

redo read/write calibration if data read is wrong

This commit is contained in:
AngeloJacobo 2023-08-17 11:27:23 +08:00
parent a8bf429bc8
commit 36c93689e5
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
rtl/ddr3_controller.v
View File

@ -16,7 +16,7 @@
// THESE DEFINES WILL BE MODIFIED AS PARAMETERS LATER ON // THESE DEFINES WILL BE MODIFIED AS PARAMETERS LATER ON
`define DDR3_1600_11_11_11 // DDR3-1600 (11-11-11) speed bin `define DDR3_1600_11_11_11 // DDR3-1600 (11-11-11) speed bin
`define RAM_4Gb //DDR3 Capacity `define RAM_8Gb //DDR3 Capacity
//`define RAM_2Gb //`define RAM_2Gb
//`define RAM_4Gb //`define RAM_4Gb
//`define RAM_8Gb //`define RAM_8Gb
@ -1516,6 +1516,9 @@ module ddr3_controller #(
end end
else begin else begin
data_start_index[lane] <= data_start_index[lane] + 8; data_start_index[lane] <= data_start_index[lane] + 8;
if(data_start_index[lane] == 56) begin
state_calibrate <= ISSUE_WRITE_1;
end
end end
DONE_CALIBRATE: begin DONE_CALIBRATE: begin
state_calibrate <= DONE_CALIBRATE; state_calibrate <= DONE_CALIBRATE;