From 18283f4436f72a857742d2ffeb91c1f64f63ff78 Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Fri, 24 May 2024 22:43:34 +0800 Subject: [PATCH] clean verilator lint by making parameters integer (instead of being inferred as real) --- rtl/ddr3_controller.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/ddr3_controller.v b/rtl/ddr3_controller.v index fcfe838..c713d2c 100644 --- a/rtl/ddr3_controller.v +++ b/rtl/ddr3_controller.v @@ -36,7 +36,7 @@ //`define RAM_8Gb module ddr3_controller #( - parameter CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface + parameter integer CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) ROW_BITS = 14, //width of DDR3 row address COL_BITS = 10, //width of DDR3 column address