replace clock wizard with PLL

example_demo/arty_s7/arty_ddr3.v

@@ -102,13 +102,13 @@
     end
      
     (* mark_debug = "true" *) wire clk_locked;
-    clk_wiz_0 clk_wiz_inst
+    clk_wiz clk_wiz_inst
     (
     // Clock out ports
     .clk_out1(i_controller_clk), //83.333 Mhz
     .clk_out2(i_ddr3_clk), // 333.333 MHz
-    .clk_out3(i_ddr3_clk_90), //200MHz
+    .clk_out3(i_ref_clk), //200MHz
-    .clk_out4(i_ref_clk), // 333.333 MHz with 90degree shift
+    .clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90degree shift
     // Status and control signals
     .reset(i_rst),
     .locked(clk_locked),
@@ -129,7 +129,7 @@
          .m_axis_tready(1),
          .rxd(rx),
          .txd(tx),
-        .prescale(1085) //9600 Baud Rate
+        .prescale(1085) //9600 Baud Rate (83.33MHz/(8*9600))
     );
     
     // DDR3 Controller 

example_demo/arty_s7/clk_wiz.v

@@ -0,0 +1,66 @@
+`timescale 1ps/1ps
+
+module clk_wiz
+ (
+  input         clk_in1,
+  output        clk_out1,
+  output        clk_out2,
+  output        clk_out3,
+  output        clk_out4,
+  input         reset,
+  output        locked
+ );
+  wire        clk_out1_clk_wiz_0;
+  wire        clk_out2_clk_wiz_0;
+  wire        clk_out3_clk_wiz_0;
+  wire        clk_out4_clk_wiz_0;
+
+  wire clkfbout;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("INTERNAL"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (10), // 100 MHz * 10 = 1000 MHz
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (12), // 1000 MHz / 12 = 83.333 MHz
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT1_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT2_DIVIDE       (5), // 1000 MHz / 5 = 200 MHz
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    .CLKOUT3_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
+    .CLKOUT3_PHASE        (90.000),
+    .CLKOUT3_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (10.000) // 100 MHz input
+  )
+  plle2_adv_inst
+   (
+    .CLKFBOUT            (clkfbout),
+    .CLKOUT0             (clk_out1_clk_wiz_0),
+    .CLKOUT1             (clk_out2_clk_wiz_0),
+    .CLKOUT2             (clk_out3_clk_wiz_0),
+    .CLKOUT3             (clk_out4_clk_wiz_0),
+    .CLKFBIN             (clkfbout),
+	.CLKIN1              (clk_in1),
+    .LOCKED              (locked),
+    .RST                 (reset)
+  );
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_clk_wiz_0));
+  BUFG clkout2_buf
+   (.O   (clk_out2),
+    .I   (clk_out2_clk_wiz_0));
+  BUFG clkout3_buf
+   (.O   (clk_out3),
+    .I   (clk_out3_clk_wiz_0));
+  BUFG clkout4_buf
+   (.O   (clk_out4),
+    .I   (clk_out4_clk_wiz_0));
+
+endmodule

example_demo/enclustra_kx2_st1/clk_wiz.v

@@ -0,0 +1,57 @@
+`timescale 1ps/1ps
+
+module clk_wiz
+ (
+  input         clk_in1,
+  output        clk_out1,
+  output        clk_out2,
+  output        clk_out3,
+  input         reset,
+  output        locked
+ );
+  wire        clk_out1_clk_wiz_0;
+  wire        clk_out2_clk_wiz_0;
+  wire        clk_out3_clk_wiz_0;
+
+  wire clkfbout;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("INTERNAL"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (8), // 100 MHz * 8 = 800 MHz
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (8), // 800 MHz / 8 = 100 MHz
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT1_DIVIDE       (2), // 800 MHz / 2 = 400 MHz
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT2_DIVIDE       (4), // 800 MHz / 4 = 200 MHz
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (10.000) // 100 MHz input
+  )
+  plle2_adv_inst
+   (
+    .CLKFBOUT            (clkfbout),
+    .CLKOUT0             (clk_out1_clk_wiz_0),
+    .CLKOUT1             (clk_out2_clk_wiz_0),
+    .CLKOUT2             (clk_out3_clk_wiz_0),
+    .CLKFBIN             (clkfbout),
+	.CLKIN1              (clk_in1),
+    .LOCKED              (locked),
+    .RST                 (reset)
+  );
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_clk_wiz_0));
+  BUFG clkout2_buf
+   (.O   (clk_out2),
+    .I   (clk_out2_clk_wiz_0));
+  BUFG clkout3_buf
+   (.O   (clk_out3),
+    .I   (clk_out3_clk_wiz_0));
+
+endmodule

example_demo/enclustra_kx2_st1/enclustra_ddr3.v

@@ -101,7 +101,7 @@
     end
      
     wire clk_locked;
-    clk_wiz_0 clk_wiz_inst
+    clk_wiz clk_wiz_inst
     (
     // Clock out ports
     .clk_out1(i_controller_clk), //100 Mhz