# DDR3_Controller (This repo will SOON be documented)
# :construction: :construction_worker_man: :construction_worker_man: UNDER CONSTRUCTION :construction_worker_man: :construction_worker_man: :construction:
Developer won't be available until end of October, but will be back by first week of November to continue this project. Planned improvements:
- User documentation
- More elaborated comments on the verilog file
- AXI interface
- Reduce logic resource (by optimizing logic and by making some parts removable)
- Pass hardware test for Arty S7 FPGA board (this is currently passing on a Kintex S7 FPGA board but ironically not yet fully tested on an Arty S7 since it does not have ODELAY which makes it unable to do write calibration FOR NOW)
