2025-01-30 12:16:11 +01:00
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ddr3_controller.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_phy.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_top.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_module.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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glbl.v,Verilog,xil_defaultlib,/home/ajacobo/incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"/glbl.v
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