2023-03-02 13:07:08 +01:00
|
|
|
if [ "$1" == "" ]
|
|
|
|
|
then
|
|
|
|
|
yosys -q -p "
|
|
|
|
|
read_verilog -sv ./rtl/ddr3_controller.v;
|
|
|
|
|
synth -top ddr3_controller"
|
|
|
|
|
|
|
|
|
|
elif [ "$1" == "iverilog" ]
|
|
|
|
|
then
|
2023-03-02 13:20:14 +01:00
|
|
|
iverilog ./rtl/ddr3_controller.v -I ./rtl/ -o .out
|
2023-03-02 13:07:08 +01:00
|
|
|
vvp .out
|
|
|
|
|
|
|
|
|
|
fi
|
|
|
|
|
|
|
|
|
|
# :set fileformat=unix
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|
|
|
|
