UberDDR3/ddr3_controller.sby

[options]
mode prove
depth 7 # minimum for 100MHz controller clk
#mode cover
#depth 50

[engines]
smtbmc

[script]
read -formal ddr3_controller.v
read -formal fwb_slave.v
prep -top ddr3_controller

[files]
./rtl/ddr3_controller.v
./rtl/fwb_slave.v
added sby file for formal verif 2023-03-02 13:11:10 +01:00			`[options]`
			`mode prove`
set depth to 7 (minimum) 2023-07-13 12:43:47 +02:00			`depth 7 # minimum for 100MHz controller clk`
add cover 2023-06-29 06:56:58 +02:00			`#mode cover`
			`#depth 50`
added sby file for formal verif 2023-03-02 13:11:10 +01:00
			`[engines]`
			`smtbmc`

			`[script]`
			`read -formal ddr3_controller.v`
add wb properties module 2023-06-22 13:44:37 +02:00			`read -formal fwb_slave.v`
added sby file for formal verif 2023-03-02 13:11:10 +01:00			`prep -top ddr3_controller`

			`[files]`
			`./rtl/ddr3_controller.v`
add wb properties module 2023-06-22 13:44:37 +02:00			`./rtl/fwb_slave.v`