Deepashree Sengupta eb0446d4e2 Write verilog escape (#394) ... * Fir for write_verilog issue 3826 Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * staToVerilog2 remove escaped_name+=ch Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * updated regression to remove \ from module name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Using helpers.tcl function to redirect results Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * add std::string and remove trailing space, update regression name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * update regression to reflect correct output verilog name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>		2026-03-02 16:48:15 -08:00
..
ConcreteLibrary.cc	rm using std::	2026-03-02 12:13:13 -08:00
ConcreteNetwork.cc	rm using std::	2026-03-02 12:13:13 -08:00
HpinDrvrLoad.cc	rel 3.0	2026-01-13 09:36:45 -07:00
Link.tcl	update copyright	2025-01-21 18:54:33 -07:00
Network.cc	rm using std::	2026-03-02 12:13:13 -08:00
Network.i	rel 3.0	2026-01-13 09:36:45 -07:00
Network.tcl	rel 3.0	2026-01-13 09:36:45 -07:00
NetworkCmp.cc	rel 3.0	2026-01-13 09:36:45 -07:00
NetworkEdit.i	Sta::netorkChangedNonSdc resolves #372	2026-01-29 16:35:54 -07:00
NetworkEdit.tcl	rel 3.0	2026-01-13 09:36:45 -07:00
ParseBus.cc	rm using std::	2026-03-02 12:13:13 -08:00
PortDirection.cc	rel 3.0	2026-01-13 09:36:45 -07:00
SdcNetwork.cc	rm using std::	2026-03-02 12:13:13 -08:00
VerilogNamespace.cc	Write verilog escape (#394)	2026-03-02 16:48:15 -08:00