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Deepashree Sengupta
eb0446d4e2
* Fir for write_verilog issue 3826 Signed-off-by: dsengupta0628 <[email protected]> * staToVerilog2 remove escaped_name+=ch Signed-off-by: dsengupta0628 <[email protected]> * updated regression to remove \ from module name Signed-off-by: dsengupta0628 <[email protected]> * Using helpers.tcl function to redirect results Signed-off-by: dsengupta0628 <[email protected]> * add std::string and remove trailing space, update regression name Signed-off-by: dsengupta0628 <[email protected]> * update regression to reflect correct output verilog name Signed-off-by: dsengupta0628 <[email protected]> --------- Signed-off-by: dsengupta0628 <[email protected]>