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https://github.com/The-OpenROAD-Project/OpenSTA.git
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Deepashree Sengupta
ef0b69091f
* support for filter in get_scene/mode Signed-off-by: dsengupta0628 <[email protected]> * fix singular G matrix issue for degenerate nets Signed-off-by: dsengupta0628 <[email protected]> * fix the mistake on existing regression- was accidentally modified Signed-off-by: dsengupta0628 <[email protected]> * make changes accounting for future SI support and address reviews Signed-off-by: dsengupta0628 <[email protected]> * simplify comment Signed-off-by: dsengupta0628 <[email protected]> * address feedbacks Signed-off-by: dsengupta0628 <[email protected]> --------- Signed-off-by: dsengupta0628 <[email protected]>
12 lines
421 B
Verilog
12 lines
421 B
Verilog
module top (clk, in0, in1, out0, out1);
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input clk, in0, in1;
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output out0, out1;
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wire q0, q1, z0, z1;
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DFFHQx4_ASAP7_75t_R r0 (.D(in0), .CLK(clk), .Q(q0));
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BUFx2_ASAP7_75t_R u0 (.A(q0), .Y(z0));
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DFFHQx4_ASAP7_75t_R t0 (.D(z0), .CLK(clk), .Q(out0));
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DFFHQx4_ASAP7_75t_R r1 (.D(in1), .CLK(clk), .Q(q1));
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BUFx2_ASAP7_75t_R u1 (.A(q1), .Y(z1));
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DFFHQx4_ASAP7_75t_R t1 (.D(z1), .CLK(clk), .Q(out1));
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endmodule
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