33 lines
1.3 KiB
Tcl
33 lines
1.3 KiB
Tcl
# Test 2: Write with remove_cells for multi-gate design
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 2: Write with remove_cells for multi-gate design
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#---------------------------------------------------------------
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puts "--- Test 2: remove_cells on multi-gate design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../dcalc/test/dcalc_multidriver_test.v
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link_design dcalc_multidriver_test
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set out_md_basic [make_result_file verilog_remove_md_basic.v]
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write_verilog $out_md_basic
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# Remove INV_X1
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set out_md_inv [make_result_file verilog_remove_md_inv.v]
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write_verilog -remove_cells {NangateOpenCellLibrary/INV_X1} $out_md_inv
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# Remove AND2_X1
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set out_md_and [make_result_file verilog_remove_md_and.v]
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write_verilog -remove_cells {NangateOpenCellLibrary/AND2_X1} $out_md_and
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# Remove NAND2_X1 and NOR2_X1
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set out_md_gates [make_result_file verilog_remove_md_gates.v]
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write_verilog -remove_cells {NangateOpenCellLibrary/NAND2_X1 NangateOpenCellLibrary/NOR2_X1} $out_md_gates
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# Compare sizes
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set sz_md [file size $out_md_basic]
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set sz_md_inv [file size $out_md_inv]
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set sz_md_and [file size $out_md_and]
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set sz_md_gates [file size $out_md_gates]
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puts "multigate sizes: basic=$sz_md inv=$sz_md_inv and=$sz_md_and gates=$sz_md_gates"
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