39 lines
1.3 KiB
Plaintext
39 lines
1.3 KiB
Plaintext
--- Test 3: write complex bus design ---
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--- roundtrip complex bus ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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complex roundtrip cells: 28
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complex roundtrip ports: 27
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roundtrip data_a[*]: 8
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roundtrip data_b[*]: 8
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roundtrip result[*]: 8
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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