22 lines
758 B
Tcl
22 lines
758 B
Tcl
# Test write_gate_spice with different cell types, rise/fall transitions,
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# and multiple simulators.
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# NOTE: All write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
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# is missing. See bug_report_missing_write_gate_spice_cmd.md.
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# Only baseline timing check remains.
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog spice_test2.v
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link_design spice_test2
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 1.0 [get_ports out1]
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set_output_delay -clock clk 1.0 [get_ports out2]
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set_input_transition 0.1 [get_ports {in1 in2}]
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puts "--- report_checks baseline ---"
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report_checks
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