OpenSTA/spice
Jaehyun Kim e5d8d8c970 test: Remove empty-body assertions and fix test issues from review feedback
Remove useless empty-body if-blocks that check file size/existence without
doing anything, replacing them with meaningful puts output where appropriate.
Split monolithic verilog test files into individual per-test files with
their own .ok golden files. Update .ok files to match actual output.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-22 18:52:36 +09:00
..
test test: Remove empty-body assertions and fix test issues from review feedback 2026-02-22 18:52:36 +09:00
WritePathSpice.cc rm using std::string from headers 2025-05-22 09:25:56 -07:00
WritePathSpice.hh update copyright 2025-01-21 18:54:33 -07:00
WriteSpice.cc WriteSpice rm dead code 2026-01-11 19:52:55 -08:00
WriteSpice.hh Verilog make pins for liberty pg_pins resolves #326 2025-11-07 11:55:43 -07:00
WriteSpice.i class Path replaces PathVertex etc 2025-03-26 18:21:03 -07:00
WriteSpice.tcl update copyright 2025-01-21 18:54:33 -07:00
Xyce.cc update copyright 2025-01-21 18:54:33 -07:00
Xyce.hh update copyright 2025-01-21 18:54:33 -07:00