123 lines
3.9 KiB
Tcl
123 lines
3.9 KiB
Tcl
# Test advanced verilog writer options for coverage improvement
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# Targets: VerilogWriter.cc (67.0% coverage)
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# - writeModules hierarchy paths
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# - writeInstBusPin / writeInstBusPinBit
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# - writeWireDcls
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# - writeAssigns
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# - findUnconnectedNetCount / findChildNCcount / findPortNCcount
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# - verilogPortDir for various directions
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Write verilog from ASAP7 design (has more complexity)
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#---------------------------------------------------------------
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puts "--- Test 1: ASAP7 write ---"
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
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read_verilog ../../test/reg1_asap7.v
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link_design top
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puts "cells: [llength [get_cells *]]"
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puts "nets: [llength [get_nets *]]"
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puts "ports: [llength [get_ports *]]"
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# Write basic
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set out1 [make_result_file verilog_advanced_out1.v]
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write_verilog $out1
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puts "PASS: basic write_verilog"
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# Write with pwr_gnd
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set out2 [make_result_file verilog_advanced_out2.v]
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write_verilog -include_pwr_gnd $out2
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puts "PASS: write_verilog -include_pwr_gnd"
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# Write with remove_cells
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set out3 [make_result_file verilog_advanced_out3.v]
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write_verilog -remove_cells {} $out3
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puts "PASS: write_verilog -remove_cells {}"
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# Compare sizes
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set sz1 [file size $out1]
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set sz2 [file size $out2]
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set sz3 [file size $out3]
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puts "basic size: $sz1"
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puts "pwr_gnd size: $sz2"
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puts "remove_cells size: $sz3"
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if { $sz2 >= $sz1 } {
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puts "PASS: pwr_gnd >= basic"
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}
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#---------------------------------------------------------------
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# Test 2: Write after network modification
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#---------------------------------------------------------------
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puts "--- Test 2: Write after modification ---"
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# Add an instance and net
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set new_net [make_net extra_net]
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set new_inst [make_instance extra_buf asap7sc7p5t_INVBUF_RVT/BUFx2_ASAP7_75t_R]
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connect_pin extra_net extra_buf/A
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set out4 [make_result_file verilog_advanced_out4.v]
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write_verilog $out4
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puts "PASS: write_verilog after adding instance"
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set sz4 [file size $out4]
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puts "modified size: $sz4"
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if { $sz4 > $sz1 } {
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puts "PASS: modified output is larger"
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}
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# Disconnect and delete
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disconnect_pin extra_net extra_buf/A
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delete_instance extra_buf
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delete_net extra_net
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#---------------------------------------------------------------
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# Test 3: Write verilog for sky130 design with attributes
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#---------------------------------------------------------------
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puts "--- Test 3: Sky130 with attributes ---"
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# Reset
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
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read_verilog ../../test/verilog_attribute.v
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link_design counter
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set out5 [make_result_file verilog_advanced_out5.v]
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write_verilog $out5
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puts "PASS: write_verilog sky130 attribute"
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set out6 [make_result_file verilog_advanced_out6.v]
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write_verilog -include_pwr_gnd $out6
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puts "PASS: write_verilog sky130 attribute -include_pwr_gnd"
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set sz5 [file size $out5]
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set sz6 [file size $out6]
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puts "sky130 basic: $sz5, pwr_gnd: $sz6"
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#---------------------------------------------------------------
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# Test 4: Write verilog for Nangate45 design
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#---------------------------------------------------------------
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puts "--- Test 4: Nangate45 write ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_test1.v
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link_design verilog_test1
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set out7 [make_result_file verilog_advanced_out7.v]
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write_verilog $out7
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puts "PASS: write_verilog nangate45"
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set out8 [make_result_file verilog_advanced_out8.v]
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write_verilog -include_pwr_gnd $out8
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puts "PASS: write_verilog nangate45 -include_pwr_gnd"
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set sz7 [file size $out7]
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set sz8 [file size $out8]
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puts "nangate45 basic: $sz7, pwr_gnd: $sz8"
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puts "ALL PASSED"
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