OpenSTA/verilog/test/verilog_specify.ok

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--- read verilog with specify/parameter ---
Warning: verilog_specify.tcl line 1, instance '*' not found.
cells: 0
nets: 4
ports: 4
PASS: read_verilog with specify/parameter
--- write_verilog ---
PASS: write_verilog after specify
PASS: output file is non-empty
ALL PASSED