165 lines
5.1 KiB
Plaintext
165 lines
5.1 KiB
Plaintext
--- query cells ---
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cells count: 2
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--- query nets ---
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nets count: 5
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--- query pins ---
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pins count: 12
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--- query ports ---
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ports count: 4
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--- create_clock ---
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PASS: clock and constraints created
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--- report_checks ---
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Startpoint: reset (input port clocked by clk)
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Endpoint: _1415_ (recovery check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ reset (in)
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0.00 0.00 ^ _1415_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
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0.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
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0.23 10.23 library recovery time
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10.23 data required time
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---------------------------------------------------------
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10.23 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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10.23 slack (MET)
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Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
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Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
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0.33 0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1)
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0.00 0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1)
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0.33 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1)
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-0.12 9.88 library setup time
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9.88 data required time
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---------------------------------------------------------
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9.88 data required time
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-0.33 data arrival time
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---------------------------------------------------------
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9.55 slack (MET)
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PASS: report_checks completed
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--- report_checks -path_delay min ---
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Startpoint: reset (input port clocked by clk)
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Endpoint: _1415_ (removal check against rising-edge clock clk)
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Path Group: asynchronous
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ reset (in)
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0.00 0.00 ^ _1415_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
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0.30 0.30 library removal time
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0.30 data required time
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---------------------------------------------------------
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0.30 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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-0.30 slack (VIOLATED)
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Startpoint: in (input port clocked by clk)
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Endpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in (in)
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0.00 0.00 ^ _1415_/D (sky130_fd_sc_hd__dfrtp_1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
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-0.03 -0.03 library hold time
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-0.03 data required time
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---------------------------------------------------------
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-0.03 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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0.03 slack (MET)
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PASS: report_checks min completed
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--- get_cells with filter ---
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dfrtp cells count: 2
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--- report_instance for first cell ---
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Instance _1415_
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Cell: sky130_fd_sc_hd__dfrtp_1
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Library: sky130_fd_sc_hd__tt_025C_1v80
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Path cells: sky130_fd_sc_hd__dfrtp_1
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Input pins:
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CLK input clk
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D input in
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RESET_B input reset
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Output pins:
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Q output mid
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Other pins:
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IQ internal (unconnected)
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IQ_N internal (unconnected)
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VGND ground (unconnected)
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VNB unknown (unconnected)
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VPB unknown (unconnected)
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VPWR power (unconnected)
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--- report_net mid ---
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Net mid
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Pin capacitance: 0.00-0.00
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Wire capacitance: 0.00
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Total capacitance: 0.00-0.00
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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_1415_/Q output (sky130_fd_sc_hd__dfrtp_1)
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Load pins
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_1416_[0]/D input (sky130_fd_sc_hd__dfrtp_1) 0.00-0.00
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--- all_inputs ---
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all_inputs count: 3
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--- all_outputs ---
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all_outputs count: 1
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--- all_clocks ---
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all_clocks count: 1
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ALL PASSED
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