106 lines
3.5 KiB
Tcl
106 lines
3.5 KiB
Tcl
# Test VerilogReader with preprocessor macro lines (`ifdef/`endif/`define/`else/`ifndef),
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# parameter declarations (scalar and bus), parameter overrides via #(...) on instances,
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# defparam statements, and parameter expressions (+, -, *, /).
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# Targets:
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# VerilogLex.ll: ^[ \t]*`.*{EOL} macro line skip
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# VerilogParse.yy: parameter, parameter '[' INT ':' INT ']', parameter_dcls,
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# parameter_dcl with STRING, parameter_expr (arithmetic ops),
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# defparam, param_values, param_value with STRING,
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# instance with parameter_values (#(...))
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# VerilogReader.cc: makeModuleInst with parameter override path,
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# makeModule, makeDcl, linkNetwork
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read verilog with preprocessor/parameter constructs
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#---------------------------------------------------------------
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puts "--- Test 1: read verilog with preproc and params ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_preproc_param.v
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link_design verilog_preproc_param
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Verify hierarchical sub-module instances
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set hier_cells [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $hier_cells]"
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puts "PASS: read verilog with preproc/param"
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#---------------------------------------------------------------
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# Test 2: Timing analysis
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#---------------------------------------------------------------
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puts "--- Test 2: timing ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {d1 d2 d3 d4}]
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set_output_delay -clock clk 0 [get_ports {q1 q2 q3 q4}]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: report_checks"
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report_checks -path_delay min
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puts "PASS: min path"
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report_checks -from [get_ports d1] -to [get_ports q1]
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puts "PASS: d1->q1"
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report_checks -from [get_ports d3] -to [get_ports q2]
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puts "PASS: d3->q2"
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report_checks -from [get_ports d1] -to [get_ports q3]
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puts "PASS: d1->q3 (through param_sub)"
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report_checks -fields {slew cap input_pins nets fanout}
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puts "PASS: report with fields"
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#---------------------------------------------------------------
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# Test 3: Write verilog and verify
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#---------------------------------------------------------------
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puts "--- Test 3: write ---"
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set out1 [make_result_file verilog_preproc_param_out.v]
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write_verilog $out1
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puts "PASS: write_verilog"
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set out2 [make_result_file verilog_preproc_param_pwr.v]
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write_verilog -include_pwr_gnd $out2
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puts "PASS: write_verilog -include_pwr_gnd"
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if { [file exists $out1] && [file size $out1] > 0 } {
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puts "PASS: output file non-empty size=[file size $out1]"
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}
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#---------------------------------------------------------------
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# Test 4: Instance and net reports
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#---------------------------------------------------------------
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puts "--- Test 4: reports ---"
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foreach inst {buf1 inv1 or1 reg1 reg2 reg3 reg4 ps1 ps2 ps3} {
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catch {report_instance $inst} msg
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}
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puts "PASS: instance reports"
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foreach net_name {n1 n2 n3 n4 n5 n6} {
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catch {report_net $net_name} msg
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}
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puts "PASS: net reports"
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#---------------------------------------------------------------
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# Test 5: Re-read to exercise module re-definition paths
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#---------------------------------------------------------------
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puts "--- Test 5: re-read ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_preproc_param.v
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link_design verilog_preproc_param
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puts "re-read cells: [llength [get_cells *]]"
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puts "PASS: re-read"
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puts "ALL PASSED"
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